mirror of
https://github.com/sxpert/hp-saturn
synced 2024-09-28 15:20:27 +02:00
357 lines
No EOL
11 KiB
Verilog
357 lines
No EOL
11 KiB
Verilog
/*
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(c) Raphaël Jacquot 2019
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This file is part of hp_saturn.
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hp_saturn is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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any later version.
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hp_saturn is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Foobar. If not, see <https://www.gnu.org/licenses/>.
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*/
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`default_nettype none
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module saturn_bus_controller (
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i_clk,
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i_clk_en,
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i_reset,
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i_phases,
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i_phase,
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i_cycle_ctr,
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o_bus_clk_en,
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o_bus_is_data,
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o_bus_nibble_out,
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i_bus_nibble_in,
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o_debug_cycle,
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o_instr_decoded,
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o_char_to_send,
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o_char_counter,
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o_char_valid,
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o_char_send,
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i_serial_busy,
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o_halt
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);
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input wire [0:0] i_clk;
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input wire [0:0] i_clk_en;
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input wire [0:0] i_reset;
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input wire [3:0] i_phases;
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input wire [1:0] i_phase;
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input wire [31:0] i_cycle_ctr;
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output reg [0:0] o_bus_clk_en;
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output reg [0:0] o_bus_is_data;
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output reg [3:0] o_bus_nibble_out;
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input wire [3:0] i_bus_nibble_in;
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output wire [0:0] o_debug_cycle;
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output wire [0:0] o_instr_decoded;
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assign o_instr_decoded = dec_instr_decoded;
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output wire [7:0] o_char_to_send;
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output wire [9:0] o_char_counter;
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output wire [0:0] o_char_valid;
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output wire [0:0] o_char_send;
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input wire [0:0] i_serial_busy;
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output wire [0:0] o_halt;
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/**************************************************************************************************
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*
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* master control unit
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*
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*************************************************************************************************/
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saturn_control_unit control_unit (
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.i_clk (i_clk),
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.i_clk_en (bus_clk_en),
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.i_reset (i_reset),
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.i_phases (i_phases),
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.i_phase (i_phase),
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.i_cycle_ctr (i_cycle_ctr),
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.i_bus_busy (bus_busy),
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.o_program_address (ctrl_unit_prog_addr),
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.i_program_address (bus_prog_addr),
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.o_program_data (ctrl_unit_prog_data),
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.o_no_read (ctrl_unit_no_read),
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.i_read (bus_read),
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.i_nibble (i_bus_nibble_in),
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.o_error (ctrl_unit_error),
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.o_alu_busy (alu_busy),
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.o_exec_unit_busy (exec_unit_busy),
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/* debugger interface */
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.o_current_pc (ctrl_current_pc),
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.o_reg_alu_mode (ctrl_reg_alu_mode),
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.o_reg_carry (ctrl_reg_carry),
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.o_reg_hst (ctrl_reg_hst),
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.o_reg_st (ctrl_reg_st),
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.o_reg_p (ctrl_reg_p),
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.i_dbg_register (dbg_register),
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.i_dbg_reg_ptr (dbg_reg_ptr),
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.o_dbg_reg_nibble (ctrl_reg_nibble),
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.i_dbg_rstk_ptr (dbg_rstk_ptr),
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.o_dbg_rstk_val (ctrl_rstk_val),
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.o_reg_rstk_ptr (ctrl_reg_rstk_ptr),
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.o_alu_reg_dest (dec_alu_reg_dest),
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.o_alu_reg_src_1 (dec_alu_reg_src_1),
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.o_alu_reg_src_2 (dec_alu_reg_src_2),
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.o_alu_imm_value (dec_alu_imm_value),
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.o_alu_opcode (dec_alu_opcode),
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.o_instr_type (dec_instr_type),
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.o_instr_decoded (dec_instr_decoded),
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.o_instr_execute (dec_instr_execute)
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);
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wire [0:0] ctrl_unit_error;
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wire [4:0] ctrl_unit_prog_addr;
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wire [5:0] ctrl_unit_prog_data;
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wire [0:0] ctrl_unit_no_read;
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wire [0:0] alu_busy;
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wire [0:0] exec_unit_busy;
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/* debugger insterface */
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wire [19:0] ctrl_current_pc;
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wire [0:0] ctrl_reg_alu_mode;
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wire [0:0] ctrl_reg_carry;
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wire [3:0] ctrl_reg_hst;
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wire [15:0] ctrl_reg_st;
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wire [3:0] ctrl_reg_p;
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wire [3:0] ctrl_reg_nibble;
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wire [19:0] ctrl_rstk_val;
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wire [2:0] ctrl_reg_rstk_ptr;
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wire [4:0] dec_alu_reg_dest;
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wire [4:0] dec_alu_reg_src_1;
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wire [4:0] dec_alu_reg_src_2;
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wire [3:0] dec_alu_imm_value;
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wire [4:0] dec_alu_opcode;
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wire [3:0] dec_instr_type;
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wire [0:0] dec_instr_decoded;
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wire [0:0] dec_instr_execute;
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/**************************************************************************************************
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*
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* debugger module
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*
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*************************************************************************************************/
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saturn_debugger debugger (
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.i_clk (i_clk),
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.i_clk_en (i_clk_en),
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.i_reset (i_reset),
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.i_phases (i_phases),
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.i_phase (i_phase),
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.i_cycle_ctr (i_cycle_ctr),
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.o_debug_cycle (dbg_debug_cycle),
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// .i_alu_busy (alu_busy),
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.i_exec_unit_busy (exec_unit_busy),
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/* debugger interface */
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.i_current_pc (ctrl_current_pc),
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.i_reg_alu_mode (ctrl_reg_alu_mode),
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.i_reg_carry (ctrl_reg_carry),
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.i_reg_hst (ctrl_reg_hst),
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.i_reg_st (ctrl_reg_st),
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.i_reg_p (ctrl_reg_p),
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.o_dbg_register (dbg_register),
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.o_dbg_reg_ptr (dbg_reg_ptr),
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.i_dbg_reg_nibble (ctrl_reg_nibble),
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.o_dbg_rstk_ptr (dbg_rstk_ptr),
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.i_dbg_rstk_val (ctrl_rstk_val),
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.i_reg_rstk_ptr (ctrl_reg_rstk_ptr),
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.i_alu_reg_dest (dec_alu_reg_dest),
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.i_alu_reg_src_1 (dec_alu_reg_src_1),
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.i_alu_reg_src_2 (dec_alu_reg_src_2),
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.i_alu_imm_value (dec_alu_imm_value),
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.i_alu_opcode (dec_alu_opcode),
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.i_instr_type (dec_instr_type),
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.i_instr_decoded (dec_instr_decoded),
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.i_instr_execute (dec_instr_execute),
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.i_bus_busy (bus_busy),
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.o_char_to_send (o_char_to_send),
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.o_char_counter (o_char_counter),
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.o_char_valid (o_char_valid),
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.o_char_send (o_char_send),
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.i_serial_busy (i_serial_busy),
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.i_bus_debug (dbg_bus_info),
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.i_bus_action (dbg_bus_action),
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.i_bus_data (dbg_bus_data)
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);
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wire [4:0] dbg_register;
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wire [3:0] dbg_reg_ptr;
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wire [2:0] dbg_rstk_ptr;
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wire [0:0] dbg_debug_cycle;
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assign o_debug_cycle = dbg_debug_cycle;
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reg [0:0] dbg_bus_info;
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reg [1:0] dbg_bus_action;
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reg [3:0] dbg_bus_data;
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/**************************************************************************************************
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*
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* the bus controller module
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*
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*************************************************************************************************/
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/*
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* local registers
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*/
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reg [0:0] bus_error;
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reg [0:0] bus_busy;
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reg [0:0] bus_read;
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wire [0:0] bus_clk_en = !o_debug_cycle && i_clk_en;
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/*
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* program list for the bus controller
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* this is used for the control unit to send the bus controller
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* the list of things that need to be done for long sequences
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*/
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reg [4:0] bus_prog_addr;
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wire [0:0] more_to_write;
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assign more_to_write = (bus_prog_addr != ctrl_unit_prog_addr);
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/*
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* this should come from the debugger
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*/
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assign o_halt = bus_error || ctrl_unit_error;
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initial begin
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dbg_bus_info = 1'b0;
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dbg_bus_action = 2'b00;
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dbg_bus_data = 4'h0;
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bus_error = 1'b0;
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bus_prog_addr = 5'd0;
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bus_busy = 1'b1;
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end
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// wire [0:0] bus_read_valid = bus_clk_en && i_phases[2] && !bus_busy && !alu_busy;
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// wire [0:0] bus_write_valid = bus_clk_en && i_phases[1] && bus_busy && !alu_busy;
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/*
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* bus chronograms
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*
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* The bus works on a 4 phase system
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*
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*/
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always @(posedge i_clk) begin
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dbg_bus_action <= 2'b11;
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dbg_bus_data <= 4'h0;
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if (bus_clk_en && !alu_busy) begin
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case (i_phases)
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4'b0001:
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begin
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/*
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* in this phase, we can send a command or data from the processor
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*/
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// $display("BUSCTRL %0d: [%d] cycle start", i_phase, i_cycle_ctr);
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if (more_to_write) begin
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$write("BUSCTRL %0d: [%d] %0d|%0d : %5b ", i_phase, i_cycle_ctr,
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bus_prog_addr, ctrl_unit_prog_addr, ctrl_unit_prog_data);
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if (ctrl_unit_prog_data[4]) $write("CMD : ");
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else $write("DATA : ");
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$write("%h\n", ctrl_unit_prog_data[3:0]);
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bus_prog_addr <= bus_prog_addr + 5'b1;
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o_bus_is_data <= !ctrl_unit_prog_data[4];
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o_bus_nibble_out <= ctrl_unit_prog_data[3:0];
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bus_read <= ctrl_unit_prog_data[5];
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o_bus_clk_en <= 1'b1;
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bus_busy <= 1'b1;
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/* data for the debugger */
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if (!ctrl_unit_prog_data[5]) begin
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dbg_bus_info <= 1'b1;
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dbg_bus_action <= { 1'b0, ctrl_unit_prog_data[4]};
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dbg_bus_data <= ctrl_unit_prog_data[3:0];
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end
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end
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/*
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* nothing to send, see if we can read, and do it
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*/
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if (!more_to_write && !ctrl_unit_no_read) begin
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// $display("BUSCTRL %0d: [%d] setting up read", i_phase, i_cycle_ctr);
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o_bus_is_data <= 1'b1;
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o_bus_clk_en <= 1'b1;
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end
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end
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4'b0010:
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begin
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/*
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* this phase is reserved for reading data from the bus
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*/
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if (o_bus_clk_en) begin
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// $display("BUSCTRL %0d: [%d] lowering bus clock_en", i_phase, i_cycle_ctr);
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o_bus_clk_en <= 1'b0;
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end
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/* memories write to the bus in this state */
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end
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4'b0100:
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begin
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/*
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* this phase is when the instruction decoder does it's job
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*/
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if (!more_to_write && bus_busy) begin
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$display("BUSCTRL %0d: [%d] done sending the entire program", i_phase, i_cycle_ctr);
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bus_busy <= 1'b0;
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end
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/* at that poing, we read data in for the debugger */
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if ((!bus_busy && !alu_busy) || bus_read) begin
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dbg_bus_info <= 1'b1;
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dbg_bus_action <= 2'b10;
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dbg_bus_data <= i_bus_nibble_in;
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$display("BUSCTRL %0d: [%d] READ %h", i_phase, i_cycle_ctr, i_bus_nibble_in);
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end
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end
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4'b1000:
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begin
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/*
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* instructions that can be handled in one clock are done here, otherwise, we start the ALU
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*/
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end
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default: begin end // other states should not exist
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endcase
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end
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if (dbg_bus_info)
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dbg_bus_info <= 1'b0;
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if (i_reset) begin
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bus_error <= 1'b0;
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bus_prog_addr <= 5'd0;
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bus_busy <= 1'b1;
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end
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end
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endmodule |