mirror of
https://github.com/sxpert/hp-saturn
synced 2024-09-28 15:20:27 +02:00
122 lines
2 KiB
Verilog
122 lines
2 KiB
Verilog
reg [31:0] instr_ctr;
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reg decode_error;
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reg debug_stop;
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reg [3:0] cycle_type;
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reg [3:0] next_cycle;
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reg read_next_pc;
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reg execute_cycle;
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reg inc_pc;
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reg read_nibble;
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reg first_nibble;
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reg [11:0] decstate;
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reg [11:0] fields_return;
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reg [3:0] regdump;
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// bus access
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reg [19:0] bus_address;
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reg [3:0] bus_command;
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reg [3:0] bus_nibble_in;
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wire [3:0] bus_nibble_out;
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wire bus_error;
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reg bus_load_pc;
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reg en_bus_load_pc;
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// should go away, the rom should work like any other bus module
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reg [7:0] display_counter;
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// internal registers
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reg [19:0] new_PC;
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reg [19:0] next_PC;
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reg [19:0] inst_start_PC;
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reg [2:0] rstk_ptr;
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reg [19:0] jump_base;
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reg [19:0] jump_offset;
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reg hex_dec;
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`define MODE_HEX 0;
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`define MODE_DEC 1;
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// data transfer registers
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reg [3:0] t_offset;
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reg [3:0] t_cnt;
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reg [3:0] t_ctr;
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reg t_dir;
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reg t_ptr;
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reg t_reg;
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reg t_ftype;
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reg [3:0] t_field;
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reg [3:0] nb_in;
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reg [3:0] nb_out;
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reg [19:0] add_out;
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// temporary stuff
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reg t_set_test;
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reg t_set_test_val;
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reg t_add_sub;
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reg [3:0] t_first;
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reg [3:0] t_last;
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// alu control
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reg [3:0] field;
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reg [1:0] field_table;
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reg [4:0] alu_op;
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reg [3:0] alu_first;
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reg [3:0] alu_last;
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reg [3:0] alu_const;
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reg [3:0] alu_reg_src1;
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reg [3:0] alu_reg_src2;
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reg [3:0] alu_reg_dest;
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reg [3:0] alu_src1;
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reg [3:0] alu_src2;
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reg [3:0] alu_res1;
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reg [3:0] alu_res2;
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reg alu_res_carry;
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reg [3:0] alu_tmp;
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reg alu_carry;
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reg alu_debug;
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reg alu_p1_halt;
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reg alu_p2_halt;
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reg alu_halt;
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reg alu_requested_halt;
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reg [11:0] alu_return;
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reg [3:0] alu_next_cycle;
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// debugger registers
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reg [19:0] dbg_op_addr;
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reg [15:0] dbg_op_code;
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reg [3:0] dbg_reg_dest;
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reg [3:0] dbg_reg_src1;
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reg [3:0] dbg_reg_src2;
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reg [3:0] dbg_field;
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reg [3:0] dbg_first;
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reg [3:0] dbg_last;
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reg [63:0] dbg_data;
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// processor registers
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reg [19:0] PC;
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reg [3:0] P;
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reg [15:0] ST;
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reg [3:0] HST;
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reg Carry;
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reg [19:0] RSTK[0:7];
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reg [19:0] D0;
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reg [19:0] D1;
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reg [63:0] A;
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reg [63:0] B;
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reg [63:0] C;
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reg [63:0] D;
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reg [63:0] R0;
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reg [63:0] R1;
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reg [63:0] R2;
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reg [63:0] R3;
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reg [63:0] R4;
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