$date
	Thu Jan 31 14:59:26 2019
$end
$version
	Icarus Verilog
$end
$timescale
	1s
$end
$scope module mask_gen_tb $end
$var reg 4 ! nw [3:0] $end
$upscope $end
$scope module mask_gen_tb $end
$var reg 4 " ns [3:0] $end
$upscope $end
$scope module mask_gen_tb $end
$var wire 64 # m [63:0] $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
bx #
bx "
bx !
$end
#10
b0 "
b100 !
#30
b111111111111111111110000 #
b1 "
#50
b1111111111111111111100000000 #
b10 "
#70
b11111111111111111111000000000000 #
b11 "
#90
b111111111111111111110000000000000000 #
b100 "
#110
b1111111111111111111100000000000000000000 #
b101 "
#130
b11111111111111111111000000000000000000000000 #
b110 "
#150
b111111111111111111110000000000000000000000000000 #
b111 "
#170
b1111111111111111111100000000000000000000000000000000 #
b1000 "
#190
b11111111111111111111000000000000000000000000000000000000 #
b1001 "
#210
b111111111111111111110000000000000000000000000000000000000000 #
b1010 "
#230
b1111111111111111111100000000000000000000000000000000000000000000 #
b1011 "
#250
b1111111111111111000000000000000000000000000000000000000000001111 #
b1100 "
#270
b1111111111110000000000000000000000000000000000000000000011111111 #
b1101 "
#290
b1111111100000000000000000000000000000000000000000000111111111111 #
b1110 "
#310
b1111000000000000000000000000000000000000000000001111111111111111 #
b1111 "