Verilog implementation of the HP saturn processor

licence: GPLv3 or later


timings:

read:
                ____      ____      ____      ____      ____
clk :      ____|    |____|    |____|    |____|    |____|    |____
                _________
address:   ____|         |_______________________________________
                     _________
data:      _________|         |__________________________________
                          
read:      ______________|_______________________________________