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oops, LSB first
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1 changed files with 9 additions and 9 deletions
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@ -64,29 +64,29 @@ reg [9:0] data_reg;
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reg [12:0] bit_delay;
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reg [12:0] bit_delay;
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initial begin
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initial begin
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bit_delay <= `BIT_DELAY_START;
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bit_delay = `BIT_DELAY_START;
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clocking_reg <= {10{1'b1}};
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clocking_reg = {10{1'b1}};
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data_reg <= {10{1'b1}};
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data_reg = {10{1'b1}};
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end
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end
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assign o_serial_busy = !clocking_reg[9];
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assign o_serial_busy = !clocking_reg[0];
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assign o_serial_tx = data_reg[9];
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assign o_serial_tx = data_reg[0];
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always @(posedge i_clk) begin
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always @(posedge i_clk) begin
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bit_delay <= bit_delay + 13'd1;
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// $display("%0d", bit_delay);
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// $display("%0d", bit_delay);
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if (i_char_valid && !o_serial_busy) begin
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if (i_char_valid && !o_serial_busy) begin
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$display("serial storing char %c", i_char_to_send);
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$display("serial storing char %c", i_char_to_send);
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clocking_reg <= 10'b0;
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clocking_reg <= 10'b0;
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data_reg <= { 1'b0, i_char_to_send, 1'b1 };
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data_reg <= { 1'b1, i_char_to_send, 1'b0 };
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bit_delay <= `BIT_DELAY_START;
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bit_delay <= `BIT_DELAY_START;
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end
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end
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if (!i_char_valid && o_serial_busy && bit_delay[`BIT_DELAY_TEST]) begin
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if (!i_char_valid && o_serial_busy && bit_delay[`BIT_DELAY_TEST]) begin
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$display("%b %b", o_serial_tx, data_reg);
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$display("%b %b", o_serial_tx, data_reg);
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clocking_reg <= { clocking_reg[8:0], 1'b1};
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clocking_reg <= { 1'b1, clocking_reg[9:1] };
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data_reg <= { data_reg[8:0], 1'b1};
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data_reg <= { 1'b1, data_reg[9:1] };
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bit_delay <= `BIT_DELAY_START;
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bit_delay <= `BIT_DELAY_START;
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end
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end
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bit_delay <= bit_delay + 13'd1;
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end
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end
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endmodule
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endmodule
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