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implement D0=(5)

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This commit is contained in:
Raphaël Jacquot 2019-03-05 06:14:38 +01:00
parent 28483afe9a
commit f3d1a4d9d4
5 changed files with 258 additions and 100 deletions
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2
saturn_bus.v
View file

@ -167,7 +167,7 @@ always @(posedge i_clk) begin
end
`ifdef SIM
if (cycle_ctr == 130) begin
if (cycle_ctr == 133) begin
bus_halt <= 1'b1;
$display("BUS %0d: [%d] enough cycles for now", phase, cycle_ctr);
end

23
saturn_control_unit.v
View file

@ -264,7 +264,12 @@ saturn_regs_pc_rstk regs_pc_rstk (
reg [0:0] reg_alu_mode;
reg [0:0] reg_CARRY;
reg [3:0] reg_A[0:15];
reg [3:0] reg_B[0:15];
reg [3:0] reg_C[0:15];
reg [3:0] reg_D[0:15];
reg [3:0] reg_D0[0:4];
reg [3:0] reg_D1[0:4];
reg [3:0] reg_HST;
reg [15:0] reg_ST;
reg [3:0] reg_P;
@ -275,7 +280,12 @@ wire [0:0] reload_PC;
always @(i_dbg_register, i_dbg_reg_ptr) begin
case (i_dbg_register)
`ALU_REG_A: o_dbg_reg_nibble <= reg_A[i_dbg_reg_ptr];
`ALU_REG_B: o_dbg_reg_nibble <= reg_B[i_dbg_reg_ptr];
`ALU_REG_C: o_dbg_reg_nibble <= reg_C[i_dbg_reg_ptr];
`ALU_REG_D: o_dbg_reg_nibble <= reg_D[i_dbg_reg_ptr];
`ALU_REG_D0: o_dbg_reg_nibble <= reg_D0[i_dbg_reg_ptr];
`ALU_REG_D1: o_dbg_reg_nibble <= reg_D1[i_dbg_reg_ptr];
default: o_dbg_reg_nibble <= 4'h0;
endcase
end
@ -327,7 +337,12 @@ always @(posedge i_clk) begin
if (just_reset || (init_counter != 0)) begin
$display("CTRL %0d: [%d] initializing registers %0d", i_phase, i_cycle_ctr, init_counter);
reg_A[init_counter] <= 4'h0;
reg_B[init_counter] <= 4'h0;
reg_C[init_counter] <= 4'h0;
reg_D[init_counter] <= 4'h0;
reg_D0[init_counter] <= 4'h0;
reg_D1[init_counter] <= 4'h0;
init_counter <= init_counter + 4'b1;
end
@ -476,12 +491,8 @@ always @(posedge i_clk) begin
`INSTR_TYPE_LOAD:
begin
case (dec_alu_reg_dest)
`ALU_REG_A: begin end
`ALU_REG_C:
begin
$display("CTRL %0d: [%d] C[%2d] <= %h", i_phase, i_cycle_ctr, dec_alu_ptr_begin, dec_alu_imm_value);
reg_C[dec_alu_ptr_begin] <= dec_alu_imm_value;
end
`ALU_REG_C: reg_C[dec_alu_ptr_begin] <= dec_alu_imm_value;
`ALU_REG_D0: reg_D0[dec_alu_ptr_begin] <= dec_alu_imm_value;
default:
begin
$display("CTRL %0d: [%d] unsupported register for load %0d", i_phase, i_cycle_ctr, dec_alu_reg_dest);

190
saturn_debugger.v
View file

@ -184,15 +184,17 @@ always @(posedge i_clk) begin
/*
* generates the registers string
* 0123456789012
* PC: xxxxx Carry: x h: @E@ rp: x RSTK7: xxxxx
* P: x HST: bbbb ST: bbbbbbbbbbbbbbbb RSTK6: xxxxx
* A: xxxxxxxxxxxxxxxx R0: xxxxxxxxxxxxxxxx RSTK5: xxxxx
* B: xxxxxxxxxxxxxxxx R1: xxxxxxxxxxxxxxxx RSTK4: xxxxx
* C: xxxxxxxxxxxxxxxx R2: xxxxxxxxxxxxxxxx RSTK3: xxxxx
* D: xxxxxxxxxxxxxxxx R3: xxxxxxxxxxxxxxxx RSTK2: xxxxx
* D0: xxxxx D1: xxxxx R4: xxxxxxxxxxxxxxxx RSTK1: xxxxx
* RSTK0: xxxxx
0123456789012345678901234567890123456789012345
* 0 | PC: xxxxx Carry: x h: @E@ rp: x RSTK7: xxxxx
* 1 | P: x HST: bbbb ST: bbbbbbbbbbbbbbbb RSTK6: xxxxx
* 2 | A: xxxxxxxxxxxxxxxx R0: xxxxxxxxxxxxxxxx RSTK5: xxxxx
* 3 | B: xxxxxxxxxxxxxxxx R1: xxxxxxxxxxxxxxxx RSTK4: xxxxx
* 4 | C: xxxxxxxxxxxxxxxx R2: xxxxxxxxxxxxxxxx RSTK3: xxxxx
* 5 | D: xxxxxxxxxxxxxxxx R3: xxxxxxxxxxxxxxxx RSTK2: xxxxx
* 6 | D0: xxxxx D1: xxxxx R4: xxxxxxxxxxxxxxxx RSTK1: xxxxx
* 7 | RSTK0: xxxxx
*
* 0000000000111111111122222222223333333333444444444455555555556666
* 0123456789012345678901234567890123456789012345678901234567890123
*
*/
if (o_debug_cycle && !debug_done) begin
@ -278,10 +280,9 @@ always @(posedge i_clk) begin
6'd4: registers_str[registers_ctr] <= hex[{1'b0, i_reg_rstk_ptr}];
6'd5: registers_str[registers_ctr] <= " ";
6'd6: registers_str[registers_ctr] <= " ";
6'd7: registers_str[registers_ctr] <= " ";
endcase
registers_reg_ptr <= registers_reg_ptr + 6'd1;
if (registers_reg_ptr == 6'd7) begin
if (registers_reg_ptr == 6'd6) begin
registers_reg_ptr <= 6'd0;
registers_state <= `DBG_REG_RSTK7_STR;
end
@ -380,15 +381,6 @@ always @(posedge i_clk) begin
registers_str[registers_ctr] <= hex[{3'b000, i_reg_st[registers_reg_ptr[3:0]]}];
registers_reg_ptr <= registers_reg_ptr - 6'd1;
if (registers_reg_ptr == 6'd0) begin
registers_reg_ptr <= 6'd0;
registers_state <= `DBG_REG_ST_SPACES;
end
end
`DBG_REG_ST_SPACES:
begin
registers_str[registers_ctr] <= " ";
registers_reg_ptr <= registers_reg_ptr + 6'd1;
if (registers_reg_ptr == 6'd2) begin
registers_reg_ptr <= 6'd0;
registers_state <= `DBG_REG_RSTK6_STR;
end
@ -396,16 +388,18 @@ always @(posedge i_clk) begin
`DBG_REG_RSTK6_STR:
begin
case (registers_reg_ptr)
6'd0: registers_str[registers_ctr] <= "R";
6'd1: registers_str[registers_ctr] <= "S";
6'd2: registers_str[registers_ctr] <= "T";
6'd3: registers_str[registers_ctr] <= "K";
6'd4: registers_str[registers_ctr] <= "6";
6'd5: registers_str[registers_ctr] <= ":";
6'd6: registers_str[registers_ctr] <= " ";
6'd0: registers_str[registers_ctr] <= " ";
6'd1: registers_str[registers_ctr] <= " ";
6'd2: registers_str[registers_ctr] <= "R";
6'd3: registers_str[registers_ctr] <= "S";
6'd4: registers_str[registers_ctr] <= "T";
6'd5: registers_str[registers_ctr] <= "K";
6'd6: registers_str[registers_ctr] <= "6";
6'd7: registers_str[registers_ctr] <= ":";
6'd8: registers_str[registers_ctr] <= " ";
endcase
registers_reg_ptr <= registers_reg_ptr + 6'd1;
if (registers_reg_ptr == 6'd6) begin
if (registers_reg_ptr == 6'd8) begin
registers_reg_ptr <= 6'd4;
o_dbg_rstk_ptr <= 3'd6;
registers_state <= `DBG_REG_RSTK6_VALUE;
@ -417,6 +411,60 @@ always @(posedge i_clk) begin
registers_reg_ptr <= registers_reg_ptr - 6'd1;
if (registers_reg_ptr == 6'd0) begin
registers_reg_ptr <= 6'd0;
registers_state <= `DBG_REG_A_STR;
end
end
`DBG_REG_A_STR:
begin
case (registers_reg_ptr)
6'd0: registers_str[registers_ctr] <= 8'd10;
6'd1: registers_str[registers_ctr] <= 8'd13;
6'd2: registers_str[registers_ctr] <= "A";
6'd3: registers_str[registers_ctr] <= ":";
6'd4: registers_str[registers_ctr] <= " ";
6'd5: registers_str[registers_ctr] <= " ";
endcase
registers_reg_ptr <= registers_reg_ptr + 6'd1;
if (registers_reg_ptr == 6'd5) begin
registers_reg_ptr <= 6'd15;
o_dbg_register <= `ALU_REG_A;
registers_state <= `DBG_REG_A_VALUE;
end
end
`DBG_REG_A_VALUE:
begin
registers_str[registers_ctr] <= hex[i_dbg_reg_nibble];
registers_reg_ptr <= registers_reg_ptr - 6'd1;
if (registers_reg_ptr == 6'd0) begin
registers_reg_ptr <= 6'd0;
o_dbg_register <= `ALU_REG_NONE;
registers_state <= `DBG_REG_B_STR;
end
end
`DBG_REG_B_STR:
begin
case (registers_reg_ptr)
6'd0: registers_str[registers_ctr] <= 8'd10;
6'd1: registers_str[registers_ctr] <= 8'd13;
6'd2: registers_str[registers_ctr] <= "B";
6'd3: registers_str[registers_ctr] <= ":";
6'd4: registers_str[registers_ctr] <= " ";
6'd5: registers_str[registers_ctr] <= " ";
endcase
registers_reg_ptr <= registers_reg_ptr + 6'd1;
if (registers_reg_ptr == 6'd5) begin
registers_reg_ptr <= 6'd15;
o_dbg_register <= `ALU_REG_B;
registers_state <= `DBG_REG_B_VALUE;
end
end
`DBG_REG_B_VALUE:
begin
registers_str[registers_ctr] <= hex[i_dbg_reg_nibble];
registers_reg_ptr <= registers_reg_ptr - 6'd1;
if (registers_reg_ptr == 6'd0) begin
registers_reg_ptr <= 6'd0;
o_dbg_register <= `ALU_REG_NONE;
registers_state <= `DBG_REG_C_STR;
end
end
@ -438,6 +486,87 @@ always @(posedge i_clk) begin
end
end
`DBG_REG_C_VALUE:
begin
registers_str[registers_ctr] <= hex[i_dbg_reg_nibble];
registers_reg_ptr <= registers_reg_ptr - 6'd1;
if (registers_reg_ptr == 6'd0) begin
registers_reg_ptr <= 6'd0;
o_dbg_register <= `ALU_REG_NONE;
registers_state <= `DBG_REG_D_STR;
end
end
`DBG_REG_D_STR:
begin
case (registers_reg_ptr)
6'd0: registers_str[registers_ctr] <= 8'd10;
6'd1: registers_str[registers_ctr] <= 8'd13;
6'd2: registers_str[registers_ctr] <= "D";
6'd3: registers_str[registers_ctr] <= ":";
6'd4: registers_str[registers_ctr] <= " ";
6'd5: registers_str[registers_ctr] <= " ";
endcase
registers_reg_ptr <= registers_reg_ptr + 6'd1;
if (registers_reg_ptr == 6'd5) begin
registers_reg_ptr <= 6'd15;
o_dbg_register <= `ALU_REG_D;
registers_state <= `DBG_REG_D_VALUE;
end
end
`DBG_REG_D_VALUE:
begin
registers_str[registers_ctr] <= hex[i_dbg_reg_nibble];
registers_reg_ptr <= registers_reg_ptr - 6'd1;
if (registers_reg_ptr == 6'd0) begin
registers_reg_ptr <= 6'd0;
o_dbg_register <= `ALU_REG_NONE;
registers_state <= `DBG_REG_D0_STR;
end
end
`DBG_REG_D0_STR:
begin
case (registers_reg_ptr)
6'd0: registers_str[registers_ctr] <= 8'd10;
6'd1: registers_str[registers_ctr] <= 8'd13;
6'd2: registers_str[registers_ctr] <= "D";
6'd3: registers_str[registers_ctr] <= "0";
6'd4: registers_str[registers_ctr] <= ":";
6'd5: registers_str[registers_ctr] <= " ";
endcase
registers_reg_ptr <= registers_reg_ptr + 6'd1;
if (registers_reg_ptr == 6'd5) begin
registers_reg_ptr <= 6'd4;
o_dbg_register <= `ALU_REG_D0;
registers_state <= `DBG_REG_D0_VALUE;
end
end
`DBG_REG_D0_VALUE:
begin
registers_str[registers_ctr] <= hex[i_dbg_reg_nibble];
registers_reg_ptr <= registers_reg_ptr - 6'd1;
if (registers_reg_ptr == 6'd0) begin
registers_reg_ptr <= 6'd0;
o_dbg_register <= `ALU_REG_NONE;
registers_state <= `DBG_REG_D1_STR;
end
end
`DBG_REG_D1_STR:
begin
case (registers_reg_ptr)
6'd0: registers_str[registers_ctr] <= " ";
6'd1: registers_str[registers_ctr] <= " ";
6'd2: registers_str[registers_ctr] <= "D";
6'd3: registers_str[registers_ctr] <= "1";
6'd4: registers_str[registers_ctr] <= ":";
6'd5: registers_str[registers_ctr] <= " ";
endcase
registers_reg_ptr <= registers_reg_ptr + 6'd1;
if (registers_reg_ptr == 6'd5) begin
registers_reg_ptr <= 6'd4;
o_dbg_register <= `ALU_REG_D1;
registers_state <= `DBG_REG_D1_VALUE;
end
end
`DBG_REG_D1_VALUE:
begin
registers_str[registers_ctr] <= hex[i_dbg_reg_nibble];
registers_reg_ptr <= registers_reg_ptr - 6'd1;
@ -455,7 +584,7 @@ always @(posedge i_clk) begin
default: registers_str[registers_ctr] <= " ";
endcase
registers_reg_ptr <= registers_reg_ptr + 6'd1;
if (registers_reg_ptr == 6'd47) begin
if (registers_reg_ptr == 6'd46) begin
registers_reg_ptr <= 6'd0;
registers_state <= `DBG_REG_RSTK0_STR;
end
@ -509,7 +638,8 @@ always @(posedge i_clk) begin
end
/*
*
* once the string is generated in the blockram above, write it out the
* serial port as fast as possible
*/
if (i_clk_en && o_debug_cycle && debug_done && !write_out) begin

115
saturn_def_debugger.v
View file

@ -14,75 +14,66 @@
`define DBG_REG_RSTK_PTR 5
`define DBG_REG_RSTK7_STR 6
`define DBG_REG_RSTK7_VALUE 7
`define DBG_REG_NL_0 8
`define DBG_REG_P 9
`define DBG_REG_HST 10
`define DBG_REG_HST_SPACES 11
`define DBG_REG_ST_STR 12
`define DBG_REG_ST_VALUE 13
`define DBG_REG_ST_SPACES 14
`define DBG_REG_RSTK6_STR 15
`define DBG_REG_RSTK6_VALUE 16
`define DBG_REG_NL_1 17
`define DBG_REG_P 8
`define DBG_REG_HST 9
`define DBG_REG_HST_SPACES 10
`define DBG_REG_ST_STR 11
`define DBG_REG_ST_VALUE 12
`define DBG_REG_RSTK6_STR 13
`define DBG_REG_RSTK6_VALUE 14
`define DBG_REG_A_STR 18
`define DBG_REG_A_VALUE 19
`define DBG_REG_A_SPACES 20
`define DBG_REG_R0_STR 21
`define DBG_REG_R0_VALUE 22
`define DBG_REG_R0_SPACES 23
`define DBG_REG_RSTK5_STR 24
`define DBG_REG_RSTK5_VALUE 25
`define DBG_REG_NL_2 26
`define DBG_REG_A_STR 16
`define DBG_REG_A_VALUE 17
`define DBG_REG_A_SPACES 18
`define DBG_REG_R0_STR 19
`define DBG_REG_R0_VALUE 20
`define DBG_REG_R0_SPACES 21
`define DBG_REG_RSTK5_STR 22
`define DBG_REG_RSTK5_VALUE 23
`define DBG_REG_B_STR 27
`define DBG_REG_B_VALUE 28
`define DBG_REG_B_SPACES 29
`define DBG_REG_R1_STR 30
`define DBG_REG_R1_VALUE 31
`define DBG_REG_R1_SPACES 32
`define DBG_REG_RSTK4_STR 33
`define DBG_REG_RSTK4_VALUE 34
`define DBG_REG_NL_3 35
`define DBG_REG_B_STR 24
`define DBG_REG_B_VALUE 25
`define DBG_REG_B_SPACES 26
`define DBG_REG_R1_STR 27
`define DBG_REG_R1_VALUE 28
`define DBG_REG_R1_SPACES 29
`define DBG_REG_RSTK4_STR 30
`define DBG_REG_RSTK4_VALUE 31
`define DBG_REG_C_STR 36
`define DBG_REG_C_VALUE 37
`define DBG_REG_C_SPACES 38
`define DBG_REG_R2_STR 39
`define DBG_REG_R2_VALUE 40
`define DBG_REG_R2_SPACES 41
`define DBG_REG_RSTK3_STR 42
`define DBG_REG_RSTK3_VALUE 43
`define DBG_REG_NL_4 44
`define DBG_REG_C_STR 32
`define DBG_REG_C_VALUE 33
`define DBG_REG_C_SPACES 34
`define DBG_REG_R2_STR 35
`define DBG_REG_R2_VALUE 36
`define DBG_REG_R2_SPACES 37
`define DBG_REG_RSTK3_STR 38
`define DBG_REG_RSTK3_VALUE 39
`define DBG_REG_D_STR 45
`define DBG_REG_D_VALUE 46
`define DBG_REG_D_SPACES 47
`define DBG_REG_R3_STR 48
`define DBG_REG_R3_VALUE 49
`define DBG_REG_R3_SPACES 50
`define DBG_REG_RSTK2_STR 51
`define DBG_REG_RSTK2_VALUE 52
`define DBG_REG_NL_5 53
`define DBG_REG_D_STR 40
`define DBG_REG_D_VALUE 41
`define DBG_REG_D_SPACES 42
`define DBG_REG_R3_STR 43
`define DBG_REG_R3_VALUE 44
`define DBG_REG_R3_SPACES 45
`define DBG_REG_RSTK2_STR 46
`define DBG_REG_RSTK2_VALUE 47
`define DBG_REG_D0_STR 54
`define DBG_REG_D0_VALUE 55
`define DBG_REG_D0_SPACES 56
`define DBG_REG_D1_STR 57
`define DBG_REG_D1_VALUE 58
`define DBG_REG_D1_SPACES 59
`define DBG_REG_R4_STR 60
`define DBG_REG_R4_VALUE 61
`define DBG_REG_R4_SPACES 62
`define DBG_REG_RSTK1_STR 63
`define DBG_REG_RSTK1_VALUE 64
`define DBG_REG_NL_6 65
`define DBG_REG_D0_STR 48
`define DBG_REG_D0_VALUE 49
`define DBG_REG_D1_STR 50
`define DBG_REG_D1_VALUE 51
`define DBG_REG_R4_STR 52
`define DBG_REG_R4_VALUE 53
`define DBG_REG_R4_SPACES 54
`define DBG_REG_RSTK1_STR 55
`define DBG_REG_RSTK1_VALUE 56
`define DBG_REG_NL_6 57
`define DBG_REG_SPACES_7 66
`define DBG_REG_RSTK0_STR 67
`define DBG_REG_RSTK0_VALUE 68
`define DBG_REG_NL_7 69
`define DBG_REG_SPACES_7 58
`define DBG_REG_RSTK0_STR 59
`define DBG_REG_RSTK0_VALUE 60
`define DBG_REG_NL_7 61
`define DBG_REG_END 127
`endif

26
saturn_inst_decoder.v
View file

@ -127,6 +127,7 @@ reg [0:0] decode_started;
*/
reg [0:0] block_0x;
reg [0:0] block_1x;
reg [0:0] block_2x;
reg [0:0] block_3x;
reg [0:0] block_8x;
@ -171,6 +172,7 @@ initial begin
decode_started = 1'b0;
block_0x = 1'b0;
block_1x = 1'b0;
block_2x = 1'b0;
block_3x = 1'b0;
block_8x = 1'b0;
@ -225,6 +227,7 @@ always @(posedge i_clk) begin
decode_started <= 1'b1;
case (i_nibble)
4'h0: block_0x <= 1'b1;
4'h1: block_1x <= 1'b1;
4'h2: block_2x <= 1'b1;
4'h3: block_3x <= 1'b1;
4'h6:
@ -277,6 +280,28 @@ always @(posedge i_clk) begin
block_0x <= 1'b0;
end
if (block_1x) begin
case (i_nibble)
4'hB:
begin
$display("DECODER %0d: [%d] D)=(5)", i_phase, i_cycle_ctr, i_nibble);
o_alu_reg_dest <= `ALU_REG_D0;
o_alu_ptr_begin <= 4'h0;
o_alu_ptr_end <= 4'h4;
load_counter <= 4'h0;
load_count <= 4'h4;
o_instr_execute <= 1'b1;
block_LOAD <= 1'b1;
end
default:
begin
$display("DECODER %0d: [%d] block_1x %h", i_phase, i_cycle_ctr, i_nibble);
o_decoder_error <= 1'b1;
end
endcase
block_1x <= 1'b0;
end
if (block_2x) begin
o_alu_reg_dest <= `ALU_REG_P;
o_alu_reg_src_1 <= `ALU_REG_IMM;
@ -474,6 +499,7 @@ always @(posedge i_clk) begin
decode_started <= 1'b0;
block_0x <= 1'b0;
block_1x <= 1'b0;
block_2x <= 1'b0;
block_3x <= 1'b0;
block_8x <= 1'b0;