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print a "." when the bus is active, but not reading

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This commit is contained in:
Raphael Jacquot 2019-03-05 06:47:02 +01:00
parent ddae7f9332
commit f12a74a917
3 changed files with 16 additions and 6 deletions
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4
saturn_bus_controller.v
View file

@ -190,7 +190,8 @@ saturn_debugger debugger (
.i_serial_busy (i_serial_busy), .i_serial_busy (i_serial_busy),
.i_bus_nibble_in (i_bus_nibble_in), .i_bus_nibble_in (i_bus_nibble_in),
.i_bus_read_valid (bus_read_valid) .i_bus_read_valid (bus_read_valid),
.i_bus_busy_valid (bus_busy_valid)
); );
wire [4:0] dbg_register; wire [4:0] dbg_register;
@ -237,6 +238,7 @@ initial begin
end end
wire [0:0] bus_read_valid = bus_clk_en && i_phases[2] && !bus_busy; wire [0:0] bus_read_valid = bus_clk_en && i_phases[2] && !bus_busy;
wire [0:0] bus_busy_valid = bus_clk_en && i_phases[2] && bus_busy;
/* /*
* bus chronograms * bus chronograms

10
saturn_debugger.v
View file

@ -67,7 +67,8 @@ module saturn_debugger (
i_serial_busy, i_serial_busy,
i_bus_nibble_in, i_bus_nibble_in,
i_bus_read_valid i_bus_read_valid,
i_bus_busy_valid
); );
input wire [0:0] i_clk; input wire [0:0] i_clk;
@ -115,6 +116,7 @@ input wire [0:0] i_serial_busy;
input wire [3:0] i_bus_nibble_in; input wire [3:0] i_bus_nibble_in;
input wire [0:0] i_bus_read_valid; input wire [0:0] i_bus_read_valid;
input wire [0:0] i_bus_busy_valid;
/************************************************************************************************** /**************************************************************************************************
* *
@ -676,6 +678,12 @@ always @(posedge i_clk) begin
o_char_valid <= 1'b1; o_char_valid <= 1'b1;
end end
if (i_bus_busy_valid) begin
o_char_send <= ~o_char_send;
o_char_to_send <= ".";
o_char_valid <= 1'b1;
end
/* clear the char clock enable */ /* clear the char clock enable */
if (o_char_valid) begin if (o_char_valid) begin
o_char_valid <= 1'b0; o_char_valid <= 1'b0;

8
saturn_top.v
View file

@ -156,16 +156,16 @@ wire [0:0] serial_busy;
/* 1/4 s */ /* 1/4 s */
`define DELAY_START 26'h20A1F0 // `define DELAY_START 26'h20A1F0
`define TEST_BIT 23 // `define TEST_BIT 23
/* 1/8 s */ /* 1/8 s */
// `define DELAY_START 26'h1050F8 // `define DELAY_START 26'h1050F8
// `define TEST_BIT 22 // `define TEST_BIT 22
/* 1/16 s */ /* 1/16 s */
// `define DELAY_START 26'h08287C `define DELAY_START 26'h08287C
// `define TEST_BIT 21 `define TEST_BIT 21
/* 1/32 s */ /* 1/32 s */
// `define DELAY_START 26'h4143E // `define DELAY_START 26'h4143E