diff --git a/decstates.v b/decstates.v
index 715f7ae..25a2d0d 100644
--- a/decstates.v
+++ b/decstates.v
@@ -11,6 +11,7 @@
 `define DEC_15X_FIELD       12'h151      //  15XX
 `define DEC_MEMAXX          12'h152      //  1[45]x[y]
 `define DEC_MEMAXX_END      12'h153      
+`define DEC_PTR_MATH        12'h160      //  1[678C]n   D[01]=D[01][+-] (n+1)
 `define DEC_D0_EQ_4N        12'h1A0      //  1B
 `define DEC_D0_EQ_5N        12'h1B0      //  1B
 `define DEC_D0_EQ_LOOP      12'h1B1      //  1Bxxxxx (exec)
diff --git a/opcodes/1[678C]n_D[01]_math_n.v b/opcodes/1[678C]n_D[01]_math_n.v
new file mode 100644
index 0000000..fe35e46
--- /dev/null
+++ b/opcodes/1[678C]n_D[01]_math_n.v
@@ -0,0 +1,18 @@
+/******************************************************************************
+ *1[678C]		D[01]=D[01][+-] (n+1)
+ *
+ *
+ */ 
+
+`DEC_PTR_MATH: begin
+    case ({t_ptr, t_add_sub})
+    2'b00: {Carry, D0} <= D0 + (nb_in + 1);
+    2'b01: {Carry, D0} <= D0 - (nb_in + 1);
+    2'b10: {Carry, D1} <= D1 + (nb_in + 1);
+    2'b11: {Carry, D1} <= D1 - (nb_in + 1);
+    endcase
+    decstate <= `DEC_START;
+`ifdef SIM
+    $display("%5h D%b=D%b%s\t%2d", inst_start_PC, t_ptr, t_ptr, t_add_sub?"-":"+", nb_in+1);
+`endif
+end
\ No newline at end of file
diff --git a/opcodes/1x.v b/opcodes/1x.v
index 12104af..badc800 100644
--- a/opcodes/1x.v
+++ b/opcodes/1x.v
@@ -11,12 +11,17 @@
     4'h3: decstate <= `DEC_13X;
     4'h4: decstate <= `DEC_14X;
     4'h5: decstate <= `DEC_15X;
+    4'h6, 4'h7, 4'h8, 4'hC: begin
+        t_ptr <= (nb_in[0] & nb_in[1]) | (nb_in[2] & nb_in[3]);
+        t_add_sub <= nb_in[3];
+        decstate <= `DEC_PTR_MATH;
+    end
     4'hA: decstate <= `DEC_D0_EQ_4N;
     4'hB: decstate <= `DEC_D0_EQ_5N;
     4'hE: decstate <= `DEC_D1_EQ_4N;
     4'hF: decstate <= `DEC_D1_EQ_5N;
     default: begin 
-        $display("ERROR : DEC_1X");
+        $display("ERROR : DEC_1X %h", nb_in);
         decode_error <= 1;    
     end
     endcase
diff --git a/saturn_core.v b/saturn_core.v
index a970415..6d142c6 100644
--- a/saturn_core.v
+++ b/saturn_core.v
@@ -118,6 +118,7 @@ reg	[19:0]	add_out;
 // temporary stuff
 reg			t_set_test;
 reg			t_set_test_val;
+reg			t_add_sub;
 
 // processor registers
 reg	[19:0]	PC;
@@ -395,6 +396,7 @@ always @(posedge dec_strobe) begin
 `include "opcodes/1x.v"
 `include "opcodes/13x_ptr_and_AC.v"
 `include "opcodes/1[45]_memaccess.v"
+`include "opcodes/1[678C]n_D[01]_math_n.v"
 `include "opcodes/1[ABEF]nnnnn_D[01]_EQ_5n.v"
 `include "opcodes/2n_P_EQ_n.v"
 `include "opcodes/3n[x...]_LC.v"