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add the block to setup registers for 0Efx

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This commit is contained in:
Raphael Jacquot 2019-02-12 15:33:04 +01:00
parent e409021f35
commit eef2d13c60
1 changed files with 141 additions and 113 deletions
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44
saturn-decoder.v
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@ -145,12 +145,15 @@ always @(posedge i_clk) begin
`ALU_REG_C: $write("C");
`ALU_REG_RSTK: $write("RSTK");
`ALU_REG_ST: if (o_alu_op!=`ALU_OP_ZERO) $write("ST");
`ALU_REG_P: $write("P");
default: $write("[dest:%d]", o_reg_dest);
endcase
case (o_alu_op)
`ALU_OP_ZERO: if (o_reg_dest==`ALU_REG_ST) $write("CLRST"); else $write("=0");
`ALU_OP_COPY: $write("=");
`ALU_OP_COPY,
`ALU_OP_INC,
`ALU_OP_DEC: $write("=");
`ALU_OP_EXCH: begin end
default: $write("[op:%d]", o_alu_op);
endcase
@ -159,12 +162,15 @@ always @(posedge i_clk) begin
`ALU_OP_COPY,
`ALU_OP_EXCH,
`ALU_OP_AND,
`ALU_OP_OR:
`ALU_OP_OR,
`ALU_OP_INC,
`ALU_OP_DEC:
case (o_reg_src1)
`ALU_REG_A: $write("A");
`ALU_REG_C: $write("C");
`ALU_REG_RSTK: $write("RSTK");
`ALU_REG_ST: $write("ST");
`ALU_REG_P: $write("P");
default: $write("[src1:%d]", o_reg_src1);
endcase
endcase
@ -186,10 +192,16 @@ always @(posedge i_clk) begin
default: $write("[src2:%d]", o_reg_src2);
endcase
end
`ALU_OP_INC: $write("+1");
`ALU_OP_DEC: $write("-1");
`ALU_OP_ZERO,
`ALU_OP_COPY,
`ALU_OP_EXCH: begin end
endcase
if (!((o_reg_dest == `ALU_REG_RSTK) || (o_reg_src1 == `ALU_REG_RSTK) ||
(o_reg_dest == `ALU_REG_ST) || (o_reg_src1 == `ALU_REG_ST ))) begin
(o_reg_dest == `ALU_REG_ST) || (o_reg_src1 == `ALU_REG_ST ) ||
(o_reg_dest == `ALU_REG_P) || (o_reg_src1 == `ALU_REG_P ))) begin
$write("\t");
case (o_field)
default: $write("[f:%d]", o_field);
@ -290,6 +302,8 @@ always @(posedge i_clk) begin
endcase
end
if (continue) begin
/******************************************************************************
*
* 0x
@ -305,7 +319,7 @@ always @(posedge i_clk) begin
*
*****************************************************************************/
if (continue && block_0x) begin
if (block_0x) begin
case (i_nibble)
4'h0, 4'h1, 4'h2, 4'h3: begin
o_ins_rtn <= 1;
@ -367,12 +381,14 @@ always @(posedge i_clk) begin
*
*****************************************************************************/
if (continue && block_0Efx && !fields_table) begin
if (block_0Efx && !fields_table) begin
o_ins_alu_op <= 1;
o_alu_op <= (!i_nibble[3])?`ALU_OP_AND:`ALU_OP_OR;
continue <= 0;
o_ins_decoded <= 1;
end
end // (continue == 1)
end
end
end
@ -391,21 +407,23 @@ always @(posedge i_clk) begin
o_reg_src2 <= 0;
end else begin
if (i_en_dec && !i_stalled) begin
// reset values on instruction decode start
if (i_en_dec && !i_stalled && !continue) begin
if (!continue) begin
o_reg_dest <= 0;
o_reg_src1 <= 0;
o_reg_src2 <= 0;
end
if (continue) begin
/************************************************************************
*
* set registers for specific instructions
*
************************************************************************/
if (i_en_dec && !i_stalled && continue) begin
if (block_0x) begin
case (i_nibble)
4'h6: begin
@ -425,13 +443,23 @@ always @(posedge i_clk) begin
o_reg_dest <= `ALU_REG_ST;
o_reg_src1 <= `ALU_REG_C;
end
4'hC, 4'hD: begin
o_reg_dest <= `ALU_REG_P;
o_reg_src1 <= `ALU_REG_P;
end
endcase
end
if (block_0Efx && !fields_table) begin
`ifdef SIM
$write("\nset registers for block_0Efx");
`endif
end
end
end
end
end
/******************************************************************************