diff --git a/.gitignore b/.gitignore index 575082a..1f2c539 100644 --- a/.gitignore +++ b/.gitignore @@ -10,3 +10,4 @@ saturn_core.ICE40.json blinky.pcf demo.blif saturn-core.json +z_saturn_test.iv diff --git a/saturn_bus.v b/saturn_bus.v index bd50135..d4c31bb 100644 --- a/saturn_bus.v +++ b/saturn_bus.v @@ -18,6 +18,8 @@ */ +`default_nettype none + module saturn_bus ( i_clk, i_reset, @@ -38,8 +40,9 @@ output wire [0:0] o_halt; saturn_hp48gx_rom hp48gx_rom ( .i_clk (i_clk), .i_reset (i_reset), + .i_phase (phase), + .i_cycle_ctr (cycle_ctr), - .i_bus_reset (ctrl_bus_reset), .i_bus_clk_en (ctrl_bus_clk_en), .i_bus_is_data (ctrl_bus_is_data), .o_bus_nibble_out (rom_bus_nibble_out), @@ -58,8 +61,10 @@ wire [3:0] rom_bus_nibble_out; saturn_bus_controller bus_controller ( .i_clk (i_clk), .i_reset (i_reset), + .i_phases (phases), + .i_phase (phase), + .i_cycle_ctr (cycle_ctr), - .o_bus_reset (ctrl_bus_reset), .o_bus_clk_en (ctrl_bus_clk_en), .o_bus_is_data (ctrl_bus_is_data), .o_bus_nibble_out (ctrl_bus_nibble_out), @@ -67,15 +72,16 @@ saturn_bus_controller bus_controller ( // more ports should show up to allow for output to the serial port of debug information + .o_debug_cycle (dbg_debug_cycle), .o_halt (ctrl_halt) ); -wire [0:0] ctrl_bus_reset; wire [0:0] ctrl_bus_clk_en; wire [0:0] ctrl_bus_is_data; wire [3:0] ctrl_bus_nibble_out; reg [3:0] ctrl_bus_nibble_in; +wire [0:0] dbg_debug_cycle; wire [0:0] ctrl_halt; /************************************************************************************************** @@ -85,8 +91,16 @@ wire [0:0] ctrl_halt; * *************************************************************************************************/ -reg bus_halt; -initial bus_halt = 0; +reg [0:0] bus_halt; +reg [3:0] phases; +reg [1:0] phase; +reg [31:0] cycle_ctr; + +initial begin + bus_halt = 1'b0; + phases = 4'b1; + cycle_ctr = 32'd0; +end assign o_halt = bus_halt || ctrl_halt; @@ -99,5 +113,27 @@ always @(*) begin ctrl_bus_nibble_in = rom_bus_nibble_out; end +always @(*) begin + phase = 2'd0; + if (phases[1]) phase = 2'd1; + if (phases[2]) phase = 2'd2; + if (phases[3]) phase = 2'd3; +end + +always @(posedge i_clk) begin + /* if we're not debugging, advance phase on each clock */ + if (!dbg_debug_cycle) begin + phases <= {phases[2:0], phases[3]}; + /* using phases[3] here becase it will be phase_0 on the next step, + * so we get to a new cycle on the first phase... + */ + cycle_ctr <= cycle_ctr + {31'b0, phases[3]}; + end + + if (i_reset) begin + phases <= 4'b1; + cycle_ctr <= 32'd0; + end +end endmodule \ No newline at end of file diff --git a/saturn_bus_controller.v b/saturn_bus_controller.v index c3b390f..c6e7364 100644 --- a/saturn_bus_controller.v +++ b/saturn_bus_controller.v @@ -18,38 +18,55 @@ */ +`default_nettype none + module saturn_bus_controller ( i_clk, i_reset, + i_phases, + i_phase, + i_cycle_ctr, - o_bus_reset, o_bus_clk_en, o_bus_is_data, o_bus_nibble_out, i_bus_nibble_in, + o_debug_cycle, o_halt ); -input wire [0:0] i_clk; -input wire [0:0] i_reset; +input wire [0:0] i_clk; +input wire [0:0] i_reset; +input wire [3:0] i_phases; +input wire [1:0] i_phase; +input wire [31:0] i_cycle_ctr; -output reg [0:0] o_bus_reset; -output reg [0:0] o_bus_clk_en; -output reg [0:0] o_bus_is_data; -output reg [3:0] o_bus_nibble_out; -input wire [3:0] i_bus_nibble_in; +output reg [0:0] o_bus_clk_en; +output reg [0:0] o_bus_is_data; +output reg [3:0] o_bus_nibble_out; +input wire [3:0] i_bus_nibble_in; -output wire [0:0] o_halt; +output wire [0:0] o_debug_cycle; +output wire [0:0] o_halt; reg [0:0] bus_error; initial bus_error = 0; +// this should come from the debugger +assign o_debug_cycle = 1'b0; assign o_halt = bus_error; +always @(posedge i_clk) begin + if (!o_debug_cycle) begin + + end - + if (i_reset) begin + bus_error <= 1'b0; + end +end endmodule \ No newline at end of file diff --git a/attic/def-buscmd.v b/saturn_def_buscmd.v similarity index 100% rename from attic/def-buscmd.v rename to saturn_def_buscmd.v diff --git a/saturn_hp48gx_rom.v b/saturn_hp48gx_rom.v index 6af81eb..a670a2c 100644 --- a/saturn_hp48gx_rom.v +++ b/saturn_hp48gx_rom.v @@ -18,27 +18,138 @@ */ +`default_nettype none + +`ifdef SIM +`define ROMBITS 20 +`else +`define ROMBITS 12 +`endif + +`include "saturn_def_buscmd.v" + module saturn_hp48gx_rom ( i_clk, i_reset, + i_phase, + i_cycle_ctr, - i_bus_reset, i_bus_clk_en, i_bus_is_data, o_bus_nibble_out, i_bus_nibble_in ); -input wire [0:0] i_clk; -input wire [0:0] i_reset; +input wire [0:0] i_clk; +input wire [0:0] i_reset; +input wire [1:0] i_phase; +input wire [31:0] i_cycle_ctr; -input wire [0:0] i_bus_reset; input wire [0:0] i_bus_clk_en; input wire [0:0] i_bus_is_data; output reg [3:0] o_bus_nibble_out; input wire [3:0] i_bus_nibble_in; -initial o_bus_nibble_out = 4'b0; +reg [3:0] rom_data[0:2**`ROMBITS-1]; +initial $readmemh("rom-gx-r.hex", rom_data, 0, 2**`ROMBITS-1); +reg [3:0] last_cmd; +reg [2:0] addr_pos_ctr; +reg [19:0] local_pc; +reg [19:0] local_dp; + +initial begin + o_bus_nibble_out = 4'b0; + last_cmd = 4'b0; + addr_pos_ctr = 3'b0; + local_pc = 20'b0; + local_dp = 20'b0; +end + +always @(posedge i_clk) begin + + if (i_bus_clk_en) begin + if (i_bus_is_data) begin + /* do things with the bits...*/ + case (last_cmd) + `BUSCMD_PC_READ: + begin + o_bus_nibble_out <= rom_data[local_pc[`ROMBITS-1:0]]; + local_pc <= local_pc + 1; + + end + `BUSCMD_DP_READ: + begin + o_bus_nibble_out <= rom_data[local_dp[`ROMBITS-1:0]]; + local_dp <= local_dp + 1; + end + `BUSCMD_PC_WRITE: local_pc <= local_pc + 1; + `BUSCMD_DP_WRITE: local_dp <= local_dp + 1; + `BUSCMD_LOAD_PC: + begin + local_pc[addr_pos_ctr*4+:4] <= i_bus_nibble_in; + addr_pos_ctr <= addr_pos_ctr + 1; + end + `BUSCMD_LOAD_DP: + begin + local_dp[addr_pos_ctr*4+:4] <= i_bus_nibble_in; + addr_pos_ctr <= addr_pos_ctr + 1; + end + default: begin end + endcase + + /* auto switch to pc read / dp read */ + if (addr_pos_ctr == 4) begin + case (last_cmd) + `BUSCMD_LOAD_PC: last_cmd <= `BUSCMD_PC_READ; + `BUSCMD_LOAD_DP: last_cmd <= `BUSCMD_DP_READ; + default: begin end + endcase + end + +`ifdef SIM + $write("ROM-GX-R %0d: [%d] ", i_phase, i_cycle_ctr); + case (last_cmd) + `BUSCMD_PC_READ: $write("PC_READ <= rom[%5h]:%h", local_pc, rom_data[local_pc]); + `BUSCMD_DP_READ: $write("DP_READ <= rom[%5h]:%h", local_dp, rom_data[local_dp]); + `BUSCMD_LOAD_PC: $write("LOAD_PC - pc %5h, %h pos %0d", local_pc, i_bus_nibble_in, addr_pos_ctr); + `BUSCMD_LOAD_DP: $write("LOAD_PC - pc %5h, %h pos %0d", local_pc, i_bus_nibble_in, addr_pos_ctr); + default: $write("last_command %h nibble %h - UNHANDLED", last_cmd, i_bus_nibble_in); + endcase + if (addr_pos_ctr == 4) begin + case (last_cmd) + `BUSCMD_LOAD_PC: $write(" auto switch to PC_READ"); + `BUSCMD_LOAD_DP: $write(" auto switch to DP_READ"); + default: begin end + endcase + end + $write("\n"); +`endif + end else begin + last_cmd <= i_bus_nibble_in; + if ((i_bus_nibble_in == `BUSCMD_LOAD_PC) || (i_bus_nibble_in == `BUSCMD_LOAD_DP)) + addr_pos_ctr <= 0; +`ifdef SIM + $write("ROM-GX-R %0d: [%d] ", i_phase, i_cycle_ctr); + case (i_bus_nibble_in) + `BUSCMD_LOAD_PC: $write("LOAD_PC"); + `BUSCMD_LOAD_DP: $write("LOAD_DP"); + `BUSCMD_CONFIGURE: $write("CONFIGURE"); + `BUSCMD_RESET: $write("RESET"); + default: begin end + endcase + $write("\n"); +`endif + end + end + + if (i_reset) begin + o_bus_nibble_out <= 4'b0; + last_cmd <= 4'b0; + addr_pos_ctr <= 3'b0; + local_pc <= 20'b0; + local_dp <= 20'b0; + end +end endmodule diff --git a/saturn_top.v b/saturn_top.v index 0b1a772..33763bc 100644 --- a/saturn_top.v +++ b/saturn_top.v @@ -18,7 +18,7 @@ */ -`default_nettype none // +`default_nettype none `ifdef SIM module saturn_top;