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we have signal !

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Raphael Jacquot 2019-03-03 18:22:48 +01:00
parent c04c770cba
commit cfd7603e96
1 changed files with 0 additions and 1 deletions
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saturn_top.v
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@ -64,7 +64,6 @@ end
always @(posedge clk) begin
test <= {test[6:0], test[7]};
$display("%b | %b", test, t_led);
if (reset) begin
clk_en <= 1'b1;