From bcb44743de4dc3ffc0a22fabde3ee9fb45267f61 Mon Sep 17 00:00:00 2001 From: Raphael Jacquot Date: Tue, 12 Feb 2019 11:22:55 +0100 Subject: [PATCH] add required bits to decode fields tables --- .gitignore | 3 +- compile | 4 +- fields.v => def_alu.v | 25 ---------- def_fields.v | 19 +++++++ run | 16 +++--- saturn-alu.v | 16 ++++++ saturn-core.ESP5.ys | 2 + saturn_core.v => saturn-core.v | 26 ++++++++-- saturn-decoder.v | 91 ++++++++++++++++++++++++++++++---- saturn_core.ESP5.ys | 2 - testrom.hex | 11 +++- 11 files changed, 162 insertions(+), 53 deletions(-) rename fields.v => def_alu.v (65%) create mode 100644 def_fields.v create mode 100644 saturn-alu.v create mode 100644 saturn-core.ESP5.ys rename saturn_core.v => saturn-core.v (92%) delete mode 100644 saturn_core.ESP5.ys diff --git a/.gitignore b/.gitignore index 00ac16c..483abe6 100644 --- a/.gitignore +++ b/.gitignore @@ -9,4 +9,5 @@ obj_dir/Vsaturn_core_classes.mk saturn_core.ICE40.json blinky.pcf demo.blif -history.txt \ No newline at end of file +history.txt +saturn-core.json diff --git a/compile b/compile index 09cab2a..96976dc 100755 --- a/compile +++ b/compile @@ -5,5 +5,5 @@ #yosys -p "synth_ecp5 -top saturn_core -json saturn_core.json" saturn_core.v -yosys saturn_core.ESP5.ys -nextpnr-ecp5 --gui --85k --speed 6 --freq 5 --lpf ulx3s_v20.lpf --textcfg empty_lfe5u-85f.config --json saturn_core.json --save saturn_core.ecp5 +yosys saturn-core.ESP5.ys +nextpnr-ecp5 --gui --85k --speed 6 --freq 5 --lpf ulx3s_v20.lpf --textcfg empty_lfe5u-85f.config --json saturn-core.json --save saturn-core.ecp5 diff --git a/fields.v b/def_alu.v similarity index 65% rename from fields.v rename to def_alu.v index 2397828..aec4989 100644 --- a/fields.v +++ b/def_alu.v @@ -1,5 +1,3 @@ -`ifndef _FIELDS -`define _FIELDS `define T_SET 0 `define T_TEST 1 @@ -10,27 +8,6 @@ `define T_PTR_0 0 `define T_PTR_1 1 -`define T_REG_A 0 -`define T_REG_C 1 - -`define T_FTYPE_FIELD 0 -`define T_TTYPE_LEN 1 - -`define T_TABLE_A 0 -`define T_TABLE_B 1 -`define T_TABLE_F 2 -`define T_TABLE_Z 3 // unused - -`define T_FIELD_P 0 -`define T_FIELD_WP 1 -`define T_FIELD_XS 2 -`define T_FIELD_X 3 -`define T_FIELD_S 4 -`define T_FIELD_M 5 -`define T_FIELD_B 6 -`define T_FIELD_W 7 -`define T_FIELD_A 15 - `define ALU_OP_ZERO 0 `define ALU_OP_COPY 1 `define ALU_OP_EXCH 2 @@ -64,5 +41,3 @@ `define ALU_REG_CST 13 `define ALU_REG_M 14 `define ALU_REG_0 15 - -`endif \ No newline at end of file diff --git a/def_fields.v b/def_fields.v new file mode 100644 index 0000000..c7a8f14 --- /dev/null +++ b/def_fields.v @@ -0,0 +1,19 @@ +`ifndef _FIELDS +`define _FIELDS + +`define FT_TABLE_a 0 +`define FT_TABLE_b 1 +`define FT_TABLE_f 2 +`define FT_TABLE_value 3 // value + +`define FT_FIELD_P 0 +`define FT_FIELD_WP 1 +`define FT_FIELD_XS 2 +`define FT_FIELD_X 3 +`define FT_FIELD_S 4 +`define FT_FIELD_M 5 +`define FT_FIELD_B 6 +`define FT_FIELD_W 7 +`define FT_FIELD_A 15 + +`endif \ No newline at end of file diff --git a/run b/run index 6c6a46c..eba6e47 100755 --- a/run +++ b/run @@ -2,15 +2,15 @@ # # licence: GPLv3 or later # -verilator -Wall -I. --top-module saturn_core -cc saturn_core.v hp48_bus.v hp48_io_ram.v hp48_rom.v bus_commands.v -VERILATOR_STATUS=$? -if [ "VERILATOR_STATUS" != "0" ] -then - echo "verilator fail" - #exit -fi +# verilator -Wall -I. --top-module saturn_core -cc saturn-core.v hp48_bus.v hp48_io_ram.v hp48_rom.v bus_commands.v +# VERILATOR_STATUS=$? +# if [ "VERILATOR_STATUS" != "0" ] +# then +# echo "verilator fail" +# #exit +# fi #iverilog -v -Wall -DSIM -o mask_gen_tb mask_gen.v -iverilog -v -Wall -DSIM -o rom_tb saturn_core.v +iverilog -v -Wall -DSIM -o rom_tb saturn-core.v IVERILOG_STATUS=$? #./mask_gen_tb echo "--------------------------------------------------------------------" diff --git a/saturn-alu.v b/saturn-alu.v new file mode 100644 index 0000000..9224982 --- /dev/null +++ b/saturn-alu.v @@ -0,0 +1,16 @@ +module saturn_alu ( + i_clk, + i_reset, + i_en_alu_prep, + i_en_alu_calc, + i_en_alu_save +); + +input wire i_clk; +input wire i_reset; +input wire i_en_alu_prep; +input wire i_en_alu_calc; +input wire i_en_alu_save; + + +endmodule diff --git a/saturn-core.ESP5.ys b/saturn-core.ESP5.ys new file mode 100644 index 0000000..792c617 --- /dev/null +++ b/saturn-core.ESP5.ys @@ -0,0 +1,2 @@ +read_verilog -I. saturn-core.v +synth_ecp5 -top saturn_core -json saturn-core.json diff --git a/saturn_core.v b/saturn-core.v similarity index 92% rename from saturn_core.v rename to saturn-core.v index d9f280f..0a3b969 100644 --- a/saturn_core.v +++ b/saturn-core.v @@ -8,6 +8,7 @@ // `include "hp48_00_bus.v" // `include "dbg_module.v" `include "saturn-decoder.v" +`include "saturn-alu.v" /************************************************************************************************** * @@ -83,7 +84,7 @@ wire ins_rstk_c; // .bus_error (bus_error) // ); -saturn_decoder i_decoder ( +saturn_decoder m_decoder ( .i_clk (clk), .i_reset (reset), .i_cycles (cycle_ctr), @@ -107,6 +108,17 @@ saturn_decoder i_decoder ( .o_ins_rstk_c (ins_rstk_c) ); +saturn_alu m_alu ( + .i_clk (clk), + .i_reset (reset), + .i_en_alu_prep (en_alu_prep), + .i_en_alu_calc (en_alu_calc), + .i_en_alu_save (en_alu_save) +); + +/* + * test rom... + */ reg [3:0] rom [0:1024]; @@ -177,9 +189,15 @@ always @(posedge clk) begin end end -// always @(posedge clk) -// if (en_debugger) -// $display(cycle_ctr); +//-------------------------------------------------------------------------------------------------- +// +// test cases +// +//-------------------------------------------------------------------------------------------------- + + + + reg [3:0] nibble_in; reg [19:0] reg_pc; diff --git a/saturn-decoder.v b/saturn-decoder.v index c45b0b3..93a4342 100644 --- a/saturn-decoder.v +++ b/saturn-decoder.v @@ -4,6 +4,8 @@ * *****************************************************************************/ +`include "def_fields.v" + module saturn_decoder( i_clk, i_reset, @@ -19,6 +21,11 @@ module saturn_decoder( o_ins_addr, o_ins_decoded, + o_fields_table, + o_field, + o_field_start, + o_field_last, + o_direction, o_ins_rtn, o_set_xm, @@ -48,6 +55,11 @@ output reg o_dec_error; output reg [19:0] o_ins_addr; output reg o_ins_decoded; +output reg [1:0] o_fields_table; +output reg [3:0] o_field; +output reg [3:0] o_field_start; +output reg [3:0] o_field_last; + // generic output reg o_direction; @@ -121,7 +133,7 @@ reg continue; reg block_0x; reg block_0Efx; -reg fields_f; +reg fields_table; always @(posedge i_clk) begin @@ -153,7 +165,11 @@ always @(posedge i_clk) begin block_0Efx <= 0; // cleanup fields table variables - fields_f <= 0; + fields_table <= 0; + o_fields_table <= 3; + o_field <= 0; + o_field_start <= 0; + o_field_last <= 0; // cleanup o_direction <= 0; @@ -219,6 +235,7 @@ always @(posedge i_clk) begin end 4'hE: begin block_0x <= 0; + o_fields_table <= `FT_TABLE_f; end default: begin `ifdef SIM @@ -227,10 +244,10 @@ always @(posedge i_clk) begin o_dec_error <= 1; end endcase - continue <= (i_nibble == 4'hE); - block_0Efx <= (i_nibble == 4'hE); - fields_f <= (i_nibble == 4'hE); - o_ins_decoded <= (i_nibble != 4'hE); + continue <= (i_nibble == 4'hE); + block_0Efx <= (i_nibble == 4'hE); + fields_table <= (i_nibble == 4'hE); + o_ins_decoded <= (i_nibble != 4'hE); end /****************************************************************************** @@ -239,8 +256,11 @@ always @(posedge i_clk) begin * * *****************************************************************************/ - if (continue && block_0Efx && !fields_f) begin + + if (continue && block_0Efx && !fields_table) begin +`ifdef SIM $display("block_0Efx: nibble %h not handled", i_nibble); +`endif continue <= 0; o_dec_error <= 1; end @@ -251,9 +271,60 @@ always @(posedge i_clk) begin * * *****************************************************************************/ - if (continue && fields_f) begin - $display("fields_f: nibble %h not handled", i_nibble); - fields_f <= 0; + +// `define DEBUG_FIELDS_TABLE + + if (continue && fields_table) begin + if (fields_table != `FT_TABLE_value) begin +`ifdef DEBUG_FIELDS_TABLE +`ifdef SIM + $display("====== fields_table | table %h | nibble %b", o_fields_table, i_nibble); + $display("table_a : %b", ((o_fields_table == `FT_TABLE_a) && (!i_nibble[3]))); + $display("table_b : %b", ((o_fields_table == `FT_TABLE_b) && ( i_nibble[3]))); + $display("table_f_cond: %b", ((!i_nibble[3]) || (i_nibble == 4'hF))); + $display("table_f : %b", ((o_fields_table == `FT_TABLE_f) && ((!i_nibble[3]) || (i_nibble == 4'hF) ))); + $display("table_f nbl : %h", {4{o_fields_table == `FT_TABLE_f}} ); + $display("table_f val : %h", (i_nibble & {4{o_fields_table == `FT_TABLE_f}}) ); + $display("case nibble : %h", ((i_nibble & 4'h7) | (i_nibble & {4{fields_table == `FT_TABLE_f}})) ); +`endif +`endif + if (((o_fields_table == `FT_TABLE_a) && (!i_nibble[3])) || + ((o_fields_table == `FT_TABLE_b) && ( i_nibble[3])) || + ((o_fields_table == `FT_TABLE_f) && ((!i_nibble[3]) || (i_nibble == 4'hF) ))) begin + case ((i_nibble & 4'h7) | (i_nibble & {4{o_fields_table == `FT_TABLE_f}})) + 4'hF: begin + if (o_fields_table == `FT_TABLE_f) begin +`ifdef SIM + $display("fields_table: field A"); +`endif + end else begin + // should never happen... +`ifdef SIM + $display("fields_table: table %h nibble %h", o_fields_table, i_nibble); +`endif + end + end + default: begin +`ifdef SIM + $display("fields_table: table %h nibble %h not handled", o_fields_table, i_nibble); +`endif + o_dec_error <= 1; + end + endcase + end else begin +`ifdef SIM + $display("fields_table: table %h invalid nibble %h", o_fields_table, i_nibble); +`endif + o_dec_error <= 1; + end + end else begin +`ifdef SIM + $display("fields_table: there is nothing to decode for table FT_TABLE_value"); +`endif + o_dec_error <= 1; + end + + fields_table <= 0; end diff --git a/saturn_core.ESP5.ys b/saturn_core.ESP5.ys deleted file mode 100644 index f27ad7d..0000000 --- a/saturn_core.ESP5.ys +++ /dev/null @@ -1,2 +0,0 @@ -read_verilog -I. saturn_core.v -synth_ecp5 -top saturn_core -json saturn_core.json diff --git a/testrom.hex b/testrom.hex index cdb0c6d..3d2dc05 100644 --- a/testrom.hex +++ b/testrom.hex @@ -7,5 +7,14 @@ 0 6 // RSTK=C 0 7 // C=RSTK -0 E D +0 E 0 0 // A=A&B P +0 E 1 0 // A=A&B WP +0 E 2 0 // A=A&B XS +0 E 3 0 // A=A&B X +0 E 4 0 // A=A&B S +0 E 5 0 // A=A&B M +0 E 6 0 // A=A&B B +0 E 7 0 // A=A&B W +0 E F 0 // A=A&B A +0 E 8 0 // invalid F // end \ No newline at end of file