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cleanups

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pipeline reading from the system ram
This commit is contained in:
Raphael Jacquot 2019-03-15 13:50:23 +01:00
parent 194415a6ed
commit b96dcd717c
5 changed files with 43 additions and 16 deletions
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11
saturn_bus.v
View file

@ -92,9 +92,12 @@ saturn_hp48gx_sysram hp48gx_sysram (
.i_clk (i_clk),
.i_clk_en (i_clk_en),
.i_reset (i_reset),
`ifdef SIM
.i_phase (phase),
.i_phases (phases),
// .i_phases (phases),
.i_cycle_ctr (cycle_ctr),
`endif
.i_phase_0 (phases[0]),
.i_debug_cycle (dbg_debug_cycle),
.i_bus_clk_en (bus_clk_en),
@ -107,7 +110,9 @@ saturn_hp48gx_sysram hp48gx_sysram (
);
wire [3:0] sysram_bus_nibble_out;
// Verilator lint_off UNUSED
wire [0:0] sysram_daisy_out;
// Verilator lint_on UNUSED
wire [0:0] sysram_active;
/**************************************************************************************************
@ -121,9 +126,11 @@ saturn_hp48gx_mmio hp48gx_mmio (
.i_clk (i_clk),
.i_clk_en (i_clk_en),
.i_reset (i_reset),
`ifdef SIM
.i_phase (phase),
.i_phases (phases),
.i_cycle_ctr (cycle_ctr),
`endif
.i_phase_0 (phases[0]),
.i_debug_cycle (dbg_debug_cycle),
.i_bus_clk_en (bus_clk_en),

1
saturn_control_unit.v
View file

@ -164,7 +164,6 @@ saturn_inst_decoder instruction_decoder(
.i_cycle_ctr (i_cycle_ctr),
.i_bus_busy (i_bus_busy),
.i_alu_busy (o_alu_busy),
.i_exec_unit_busy (o_exec_unit_busy),
.i_nibble (i_nibble),

14
saturn_hp48gx_mmio.v
View file

@ -22,9 +22,11 @@ module saturn_hp48gx_mmio (
i_clk,
i_clk_en,
i_reset,
`ifdef SIM
i_phase,
i_phases,
i_cycle_ctr,
`endif
i_phase_0,
i_debug_cycle,
i_bus_clk_en,
@ -42,9 +44,11 @@ module saturn_hp48gx_mmio (
input wire [0:0] i_clk;
input wire [0:0] i_clk_en;
input wire [0:0] i_reset;
`ifdef SIM
input wire [1:0] i_phase;
input wire [3:0] i_phases;
input wire [31:0] i_cycle_ctr;
`endif
input wire [0:0] i_phase_0;
input wire [0:0] i_debug_cycle;
/**************************************************************************************************
@ -137,9 +141,9 @@ wire [19:0] access_pointer = pointer - base_addr;
wire [`MMIO_BITS-1:0] address = access_pointer[`MMIO_BITS-1:0];
wire [0:0] gen_active = i_clk_en && !i_debug_cycle && i_phases[0] && (do_read || do_write);
wire [0:0] can_read = i_bus_clk_en && i_clk_en && i_bus_is_data && do_read && active;
wire [0:0] can_write = i_bus_clk_en && i_clk_en && i_bus_is_data && do_write && active;
wire [0:0] gen_active = i_clk_en && !i_debug_cycle && i_phase_0 && (do_read || do_write);
wire [0:0] can_read = i_bus_clk_en && i_bus_is_data && do_read && active;
wire [0:0] can_write = i_bus_clk_en && i_bus_is_data && do_write && active;
/*
* reading and writing to I/O registers

31
saturn_hp48gx_sysram.v
View file

@ -22,9 +22,12 @@ module saturn_hp48gx_sysram (
i_clk,
i_clk_en,
i_reset,
`ifdef SIM
i_phase,
i_phases,
// i_phases,
i_cycle_ctr,
`endif
i_phase_0,
i_debug_cycle,
i_bus_clk_en,
@ -39,9 +42,12 @@ module saturn_hp48gx_sysram (
input wire [0:0] i_clk;
input wire [0:0] i_clk_en;
input wire [0:0] i_reset;
`ifdef SIM
input wire [1:0] i_phase;
input wire [3:0] i_phases;
//input wire [3:0] i_phases;
input wire [31:0] i_cycle_ctr;
`endif
input wire [0:0] i_phase_0;
input wire [0:0] i_debug_cycle;
/**************************************************************************************************
@ -73,6 +79,7 @@ reg [19:0] local_pc;
reg [19:0] local_dp;
reg [0:0] pc_active;
reg [0:0] dp_active;
reg [3:0] read_nibble;
reg [0:0] base_conf;
reg [0:0] length_conf;
@ -130,9 +137,10 @@ wire [19:0] access_pointer = pointer - base_addr;
wire [`SYSRAM_BITS-1:0] address = access_pointer[`SYSRAM_BITS-1:0];
wire [0:0] gen_active = i_clk_en && !i_debug_cycle && i_phases[0] && (do_read || do_write);
wire [0:0] can_read = i_bus_clk_en && i_clk_en && i_bus_is_data && do_read && configured && active;
wire [0:0] can_write = i_bus_clk_en && i_clk_en && i_bus_is_data && do_write && configured && active;
wire [0:0] gen_active = i_clk_en && !i_debug_cycle && i_phase_0 && (do_read || do_write);
wire [0:0] pre_read = i_clk_en && i_phase_0 && !i_debug_cycle && do_read;
wire [0:0] can_read = i_bus_clk_en && i_bus_is_data && do_read && active;
wire [0:0] can_write = i_bus_clk_en && i_bus_is_data && do_write && active;
/*
* reading and writing to I/O registers
@ -154,9 +162,18 @@ always @(posedge i_clk) begin
end
end
always @(posedge i_clk) begin
if (pre_read) begin
`ifdef SIM
$display("ROM-GX-R %0d: [%d] pre_read %h <= rom[%5h]", i_phase, i_cycle_ctr, sysram_data[address], address);
`endif
read_nibble <= sysram_data[address];
end
end
always @(posedge i_clk) begin
if (can_read)
o_bus_nibble_out <= sysram_data[address];
o_bus_nibble_out <= read_nibble;
end
always @(posedge i_clk) begin
@ -165,6 +182,8 @@ always @(posedge i_clk) begin
end
end
`ifdef SIM
wire [3:0] imm_nibble = sysram_data[address];
`endif

2
saturn_inst_decoder.v
View file

@ -31,7 +31,6 @@ module saturn_inst_decoder (
i_cycle_ctr,
i_bus_busy,
i_alu_busy,
i_exec_unit_busy,
i_nibble,
@ -72,7 +71,6 @@ input wire [1:0] i_phase;
input wire [31:0] i_cycle_ctr;
input wire [0:0] i_bus_busy;
input wire [0:0] i_alu_busy;
input wire [0:0] i_exec_unit_busy;
input wire [3:0] i_nibble;