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make things more readable

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This commit is contained in:
Raphael Jacquot 2019-02-11 11:29:31 +01:00
parent 8b63d25e8f
commit b39c56a43c
5 changed files with 32 additions and 16 deletions
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3
fields.v
View file

@ -39,6 +39,9 @@
`define ALU_OP_2CMPL 5 `define ALU_OP_2CMPL 5
`define ALU_OP_1CMPL 6 `define ALU_OP_1CMPL 6
`define ALU_OP_INC 8 `define ALU_OP_INC 8
`define ALU_OP_DEC 9
`define ALU_OP_ADD 10
`define ALU_OP_SUB 11
`define ALU_OP_TEST_EQ 12 `define ALU_OP_TEST_EQ 12
`define ALU_OP_TEST_NEQ 13 `define ALU_OP_TEST_NEQ 13

13
opcodes/B[ab]x.v
View file

@ -10,17 +10,18 @@
`include "fields.v" `include "fields.v"
`DEC_Bxx_EXEC: begin `DEC_Bxx_EXEC: begin
if (!field_table[0]) begin if (!field_table[0]) begin // table a
if (!nb_in[3]) begin if (!nb_in[3]) begin //
alu_reg_dest <= {2'b0, nb_in[1:0]}; alu_reg_dest <= reg_ABCD;
alu_reg_src1 <= {2'b0, nb_in[1:0]}; alu_reg_src1 <= reg_ABCD;
if (!nb_in[2]) begin if (!nb_in[2]) begin
alu_reg_src2 <= reg_BCAC;
alu_op <= `ALU_OP_SUB;
end else alu_op <= `ALU_OP_INC; end else alu_op <= `ALU_OP_INC;
end else begin end else begin // table b
$display("Bxx table 'a' not handled yet"); $display("Bxx table 'a' not handled yet");
decode_error <= 1; decode_error <= 1;
end end
end else begin end else begin
alu_reg_dest <= {2'b0, nb_in[1:0]}; alu_reg_dest <= {2'b0, nb_in[1:0]};
$display("Bxx table 'b' not handled yet"); $display("Bxx table 'b' not handled yet");

15
opcodes/Dx_regs_field_A.v
View file

@ -15,23 +15,22 @@
case (nb_in[3:2]) case (nb_in[3:2])
2'b00: begin 2'b00: begin
alu_op <= `ALU_OP_ZERO; alu_op <= `ALU_OP_ZERO;
alu_reg_dest <= {2'b00, nb_in[1:0]}; alu_reg_dest <= reg_ABCD;
end end
2'b01: begin 2'b01: begin
alu_op <= `ALU_OP_COPY; alu_op <= `ALU_OP_COPY;
alu_reg_dest <= {2'b00, nb_in[1:0]}; alu_reg_dest <= reg_ABCD;
alu_reg_src1 <= {2'b00, nb_in[0], !(nb_in[1] || nb_in[0])}; alu_reg_src1 <= reg_BCAC;
end end
2'b10: begin 2'b10: begin
alu_op <= `ALU_OP_COPY; alu_op <= `ALU_OP_COPY;
alu_reg_dest <= {2'b00, nb_in[0], !(nb_in[1] || nb_in[0])}; alu_reg_dest <= reg_BCAC;
alu_reg_src1 <= {2'b00, nb_in[1:0]}; alu_reg_src1 <= reg_ABCD;
end end
2'b11: begin 2'b11: begin
alu_op <= `ALU_OP_EXCH; alu_op <= `ALU_OP_EXCH;
alu_reg_dest <= {2'b00, nb_in[1] && nb_in[0], (!nb_in[1]) && nb_in[0]}; alu_reg_dest <= reg_ABAC;
alu_reg_src1 <= {2'b00, nb_in[1] || nb_in[0], (!nb_in[1]) ^ nb_in[0]}; alu_reg_src1 <= reg_BCCD;
alu_halt <= 1;
end end
endcase endcase
next_cycle <= `BUSCMD_NOP; next_cycle <= `BUSCMD_NOP;

4
opcodes/Fx.v
View file

@ -11,13 +11,13 @@
field <= `T_FIELD_A; field <= `T_FIELD_A;
alu_first <= 0; alu_first <= 0;
alu_last <= 4; alu_last <= 4;
alu_reg_dest <= {2'b00, nb_in[1:0]}; alu_reg_dest <= reg_ABCD;
if (!nb_in[3]) begin if (!nb_in[3]) begin
$display("F%h shifts not implemented"); $display("F%h shifts not implemented");
decode_error <= 1; decode_error <= 1;
end else begin end else begin
alu_reg_src1 <= {2'b00, nb_in[1:0]}; alu_reg_src1 <= reg_ABCD;
alu_op <= nb_in[2]?`ALU_OP_1CMPL:`ALU_OP_2CMPL; alu_op <= nb_in[2]?`ALU_OP_1CMPL:`ALU_OP_2CMPL;
end end
alu_debug <= 1; alu_debug <= 1;

13
saturn_core.v
View file

@ -410,6 +410,19 @@ end
`include "decstates.v" `include "decstates.v"
/*
* order of register in 4 op blocs has several common combinations
*/
wire [3:0] reg_ABCD;
wire [3:0] reg_BCAC;
wire [3:0] reg_ABAC;
wire [3:0] reg_BCCD;
assign reg_ABCD = {2'b00, nb_in[1:0]};
assign reg_BCAC = {2'b00, nb_in[0], !(nb_in[1] || nb_in[0])};
assign reg_ABAC = {2'b00, nb_in[1] && nb_in[0], (!nb_in[1]) && nb_in[0]};
assign reg_BCCD = {2'b00, nb_in[1] || nb_in[0], (!nb_in[1]) ^ nb_in[0]};
always @(posedge dec_strobe) begin always @(posedge dec_strobe) begin
if (alu_requested_halt) decode_error <= 1; if (alu_requested_halt) decode_error <= 1;
if ((next_cycle == `BUSCMD_LOAD_PC)| if ((next_cycle == `BUSCMD_LOAD_PC)|