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fix the compilation for proper use of clk_25mhz signal as clock

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This commit is contained in:
Raphael Jacquot 2019-03-03 13:03:36 +01:00
parent 9cb1618acb
commit a6d5491619
3 changed files with 8 additions and 3 deletions
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2
compile
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@ -11,4 +11,4 @@ echo "--------------------------------------------------------------------"
echo "YOSYS_STATUS ${YOSYS_STATUS}"
echo "--------------------------------------------------------------------"
nextpnr-ecp5 --gui --85k --speed 6 --freq 5 --lpf ulx3s_v20.lpf --textcfg empty_lfe5u-85f.config --json z_saturn_test.json --save z_saturn_test.ecp5
nextpnr-ecp5 --gui --85k --speed 6 --freq 5 --lpf ulx3s_v20.lpf --json z_saturn_test.json --save z_saturn_test.ecp5

7
saturn_top.v
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@ -33,18 +33,23 @@ input wire [0:0] clk_25mhz;
input wire [6:0] btn;
output reg [7:0] led;
`ifdef SIM
wire [0:0] clk;
`endif
wire [0:0] reset;
wire [0:0] halt;
assign clk = clk_25mhz;
assign reset = btn[0];
assign led[0] = halt;
`endif
saturn_bus main_bus (
`ifdef SIM
.i_clk (clk),
`else
.i_clk (clk_25mhz),
`endif
.i_reset (reset),
.o_halt (halt)
);

2
ulx3s_v20.lpf
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@ -9,7 +9,7 @@ FREQUENCY PORT "clk_25mhz" 25 MHZ;
# JTAG and SPI FLASH voltage 3.3V and options to boot from SPI flash
# write to FLASH possible any time from JTAG:
SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 MASTER_SPI_PORT=ENABLE SLAVE_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE;
SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=OFF MCCLK_FREQ=62 MASTER_SPI_PORT=ENABLE SLAVE_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE;
# write to FLASH possible from user bitstream:
# SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 MASTER_SPI_PORT=DISABLE SLAVE_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE;