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implement bus trasfers debugging

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This commit is contained in:
Raphael Jacquot 2019-03-06 18:19:02 +01:00
parent 6d940c7f95
commit 9549b53edc
2 changed files with 65 additions and 20 deletions
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37
saturn_bus_controller.v
View file

@ -194,9 +194,9 @@ saturn_debugger debugger (
.o_char_send (o_char_send), .o_char_send (o_char_send),
.i_serial_busy (i_serial_busy), .i_serial_busy (i_serial_busy),
.i_bus_nibble_in (i_bus_nibble_in), .i_bus_debug (dbg_bus_info),
.i_bus_read_valid (bus_read_valid), .i_bus_action (dbg_bus_action),
.i_bus_busy_valid (bus_busy_valid) .i_bus_data (dbg_bus_data)
); );
wire [4:0] dbg_register; wire [4:0] dbg_register;
@ -206,6 +206,10 @@ wire [2:0] dbg_rstk_ptr;
wire [0:0] dbg_debug_cycle; wire [0:0] dbg_debug_cycle;
assign o_debug_cycle = dbg_debug_cycle; assign o_debug_cycle = dbg_debug_cycle;
reg [0:0] dbg_bus_info;
reg [1:0] dbg_bus_action;
reg [3:0] dbg_bus_data;
/************************************************************************************************** /**************************************************************************************************
* *
* the bus controller module * the bus controller module
@ -237,13 +241,16 @@ assign more_to_write = (bus_prog_addr != ctrl_unit_prog_addr);
assign o_halt = bus_error || ctrl_unit_error; assign o_halt = bus_error || ctrl_unit_error;
initial begin initial begin
dbg_bus_info = 1'b0;
dbg_bus_action = 2'b00;
dbg_bus_data = 4'h0;
bus_error = 1'b0; bus_error = 1'b0;
bus_prog_addr = 5'd0; bus_prog_addr = 5'd0;
bus_busy = 1'b1; bus_busy = 1'b1;
end end
wire [0:0] bus_read_valid = bus_clk_en && i_phases[2] && !bus_busy && !alu_busy; // wire [0:0] bus_read_valid = bus_clk_en && i_phases[2] && !bus_busy && !alu_busy;
wire [0:0] bus_busy_valid = bus_clk_en && i_phases[2] && bus_busy && !alu_busy; // wire [0:0] bus_write_valid = bus_clk_en && i_phases[1] && bus_busy && !alu_busy;
/* /*
* bus chronograms * bus chronograms
@ -253,6 +260,8 @@ wire [0:0] bus_busy_valid = bus_clk_en && i_phases[2] && bus_busy && !alu_busy;
*/ */
always @(posedge i_clk) begin always @(posedge i_clk) begin
dbg_bus_action <= 2'b11;
dbg_bus_data <= 4'h0;
if (bus_clk_en && !alu_busy) begin if (bus_clk_en && !alu_busy) begin
case (i_phases) case (i_phases)
4'b0001: 4'b0001:
@ -272,6 +281,11 @@ always @(posedge i_clk) begin
o_bus_nibble_out <= ctrl_unit_prog_data[3:0]; o_bus_nibble_out <= ctrl_unit_prog_data[3:0];
o_bus_clk_en <= 1'b1; o_bus_clk_en <= 1'b1;
bus_busy <= 1'b1; bus_busy <= 1'b1;
/* data for the debugger */
dbg_bus_info <= 1'b1;
dbg_bus_action <= { 1'b0, ctrl_unit_prog_data[4]};
dbg_bus_data <= ctrl_unit_prog_data[3:0];
end end
/* /*
* nothing to send, see if we can read, and do it * nothing to send, see if we can read, and do it
@ -291,6 +305,8 @@ always @(posedge i_clk) begin
// $display("BUSCTRL %0d: [%d] lowering bus clock_en", i_phase, i_cycle_ctr); // $display("BUSCTRL %0d: [%d] lowering bus clock_en", i_phase, i_cycle_ctr);
o_bus_clk_en <= 1'b0; o_bus_clk_en <= 1'b0;
end end
/* memories write to the bus in this state */
end end
4'b0100: 4'b0100:
begin begin
@ -301,6 +317,14 @@ always @(posedge i_clk) begin
$display("BUSCTRL %0d: [%d] done sending the entire program", i_phase, i_cycle_ctr); $display("BUSCTRL %0d: [%d] done sending the entire program", i_phase, i_cycle_ctr);
bus_busy <= 1'b0; bus_busy <= 1'b0;
end end
/* at that poing, weread data in for the debugger */
if (!bus_busy && !alu_busy) begin
dbg_bus_info <= 1'b1;
dbg_bus_action <= 2'b10;
dbg_bus_data <= i_bus_nibble_in;
$display("BUSCTRL %0d: [%d] READ %h", i_phase, i_cycle_ctr, i_bus_nibble_in);
end
end end
4'b1000: 4'b1000:
begin begin
@ -312,6 +336,9 @@ always @(posedge i_clk) begin
endcase endcase
end end
if (dbg_bus_info)
dbg_bus_info <= 1'b0;
if (i_reset) begin if (i_reset) begin
bus_error <= 1'b0; bus_error <= 1'b0;
bus_prog_addr <= 5'd0; bus_prog_addr <= 5'd0;

38
saturn_debugger.v
View file

@ -67,9 +67,9 @@ module saturn_debugger (
o_char_send, o_char_send,
i_serial_busy, i_serial_busy,
i_bus_nibble_in, i_bus_debug,
i_bus_read_valid, i_bus_action,
i_bus_busy_valid i_bus_data
); );
input wire [0:0] i_clk; input wire [0:0] i_clk;
@ -116,9 +116,9 @@ output reg [0:0] o_char_valid;
output reg [0:0] o_char_send; output reg [0:0] o_char_send;
input wire [0:0] i_serial_busy; input wire [0:0] i_serial_busy;
input wire [3:0] i_bus_nibble_in; input wire [0:0] i_bus_debug;
input wire [0:0] i_bus_read_valid; input wire [1:0] i_bus_action;
input wire [0:0] i_bus_busy_valid; input wire [3:0] i_bus_data;
/************************************************************************************************** /**************************************************************************************************
* *
@ -129,6 +129,10 @@ input wire [0:0] i_bus_busy_valid;
reg [8:0] counter; reg [8:0] counter;
reg [0:0] write_out; reg [0:0] write_out;
/* do we have some bus data to write ? */
reg [0:0] write_bus_data;
reg [3:0] bus_data_save;
wire [0:0] debug_done; wire [0:0] debug_done;
assign debug_done = registers_done; assign debug_done = registers_done;
@ -168,6 +172,8 @@ initial begin
registers_done = 1'b0; registers_done = 1'b0;
o_char_valid = 1'b0; o_char_valid = 1'b0;
o_char_send = 1'b0; o_char_send = 1'b0;
write_bus_data = 1'b0;
bus_data_save = 4'h0;
// $monitor ("i_clk_en %b | i_phases[3] %b | i_instr_decoded %b | debug_done %b | i_alu_busy %b", // $monitor ("i_clk_en %b | i_phases[3] %b | i_instr_decoded %b | debug_done %b | i_alu_busy %b",
// i_clk_en, i_phases[3], i_instr_decoded, debug_done, i_alu_busy); // i_clk_en, i_phases[3], i_instr_decoded, debug_done, i_alu_busy);
@ -677,16 +683,26 @@ always @(posedge i_clk) begin
/* /*
* dumps nibbles read from the bus * dumps nibbles read from the bus
*/ */
if (i_bus_read_valid) begin
if (i_bus_debug) begin
o_char_send <= ~o_char_send; o_char_send <= ~o_char_send;
o_char_to_send <= hex[i_bus_nibble_in]; case (i_bus_action)
2'b00: o_char_to_send <= "w";
2'b01: o_char_to_send <= "c";
2'b10: o_char_to_send <= "r";
2'b11: o_char_to_send <= ".";
endcase
o_char_valid <= 1'b1; o_char_valid <= 1'b1;
write_bus_data <= 1'b1;
bus_data_save <= i_bus_data;
end end
if (i_bus_busy_valid) begin /* send the hex character */
if (write_bus_data && !o_char_valid && !i_serial_busy) begin
o_char_send <= ~o_char_send; o_char_send <= ~o_char_send;
o_char_to_send <= "."; o_char_to_send <= hex[bus_data_save];
o_char_valid <= 1'b1; o_char_valid <= 1'b1;
write_bus_data <= 1'b0;
end end
/* clear the char clock enable */ /* clear the char clock enable */
@ -704,6 +720,8 @@ always @(posedge i_clk) begin
registers_done <= 1'b0; registers_done <= 1'b0;
write_out <= 1'b0; write_out <= 1'b0;
o_char_valid <= 1'b0; o_char_valid <= 1'b0;
write_bus_data <= 1'b0;
bus_data_save <= 4'h0;
end end
end end