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starts complete rewrite

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This commit is contained in:
Raphael Jacquot 2019-02-24 23:30:57 +01:00
parent 570807cf61
commit 8866b8c175
8 changed files with 374 additions and 2 deletions
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0
saturn-core.ESP5.ys → make_saturn.ESP5.ys
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0
saturn_core.ICE40.ys → make_saturn.ICE40.ys
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7
run.sh
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@ -10,7 +10,10 @@
# #exit
# fi
#iverilog -v -Wall -DSIM -o mask_gen_tb mask_gen.v
iverilog -v -g2005-sv -gassertions -Wall -DSIM -o rom_tb saturn_core.v
iverilog -v -Wall -DSIM -o z_saturn_test.iv -s saturn_top \
saturn_top.v \
saturn_bus.v saturn_hp48gx_rom.v \
saturn_bus_controller.v
IVERILOG_STATUS=$?
#./mask_gen_tb
echo "--------------------------------------------------------------------"
@ -18,7 +21,7 @@ echo "IVERILOG_STATUS ${IVERILOG_STATUS}"
echo "--------------------------------------------------------------------"
if [ "${IVERILOG_STATUS}" = "0" ]
then
./rom_tb
./z_saturn_test.iv
fi
#vvp mask_gen_tb -lxt2
#gtkwave output.vcd

103
saturn_bus.v Normal file
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@ -0,0 +1,103 @@
/*
(c) Raphaël Jacquot 2019
This file is part of hp_saturn.
hp_saturn is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
any later version.
hp_saturn is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with Foobar. If not, see <https://www.gnu.org/licenses/>.
*/
module saturn_bus (
i_clk,
i_reset,
o_halt
);
input wire [0:0] i_clk;
input wire [0:0] i_reset;
output wire [0:0] o_halt;
/**************************************************************************************************
*
* this is the main firmware rom module
* this module is always active, there is no configuration.
*
*************************************************************************************************/
saturn_hp48gx_rom hp48gx_rom (
.i_clk (i_clk),
.i_reset (i_reset),
.i_bus_reset (ctrl_bus_reset),
.i_bus_clk_en (ctrl_bus_clk_en),
.i_bus_is_data (ctrl_bus_is_data),
.o_bus_nibble_out (rom_bus_nibble_out),
.i_bus_nibble_in (ctrl_bus_nibble_out)
);
wire [3:0] rom_bus_nibble_out;
/**************************************************************************************************
*
* the main processor is hidden behind this bus controller device
*
*
*************************************************************************************************/
saturn_bus_controller bus_controller (
.i_clk (i_clk),
.i_reset (i_reset),
.o_bus_reset (ctrl_bus_reset),
.o_bus_clk_en (ctrl_bus_clk_en),
.o_bus_is_data (ctrl_bus_is_data),
.o_bus_nibble_out (ctrl_bus_nibble_out),
.i_bus_nibble_in (ctrl_bus_nibble_in),
// more ports should show up to allow for output to the serial port of debug information
.o_halt (ctrl_halt)
);
wire [0:0] ctrl_bus_reset;
wire [0:0] ctrl_bus_clk_en;
wire [0:0] ctrl_bus_is_data;
wire [3:0] ctrl_bus_nibble_out;
reg [3:0] ctrl_bus_nibble_in;
wire [0:0] ctrl_halt;
/**************************************************************************************************
*
* priority logic for the bus
*
*
*************************************************************************************************/
reg bus_halt;
initial bus_halt = 0;
assign o_halt = bus_halt || ctrl_halt;
/* handles modules priority
* goes through all modules
* if the module is active, this is the one giving out it's data
* the last active module wins
*/
always @(*) begin
ctrl_bus_nibble_in = rom_bus_nibble_out;
end
endmodule

55
saturn_bus_controller.v Normal file
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@ -0,0 +1,55 @@
/*
(c) Raphaël Jacquot 2019
This file is part of hp_saturn.
hp_saturn is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
any later version.
hp_saturn is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with Foobar. If not, see <https://www.gnu.org/licenses/>.
*/
module saturn_bus_controller (
i_clk,
i_reset,
o_bus_reset,
o_bus_clk_en,
o_bus_is_data,
o_bus_nibble_out,
i_bus_nibble_in,
o_halt
);
input wire [0:0] i_clk;
input wire [0:0] i_reset;
output reg [0:0] o_bus_reset;
output reg [0:0] o_bus_clk_en;
output reg [0:0] o_bus_is_data;
output reg [3:0] o_bus_nibble_out;
input wire [3:0] i_bus_nibble_in;
output wire [0:0] o_halt;
reg [0:0] bus_error;
initial bus_error = 0;
assign o_halt = bus_error;
endmodule

44
saturn_hp48gx_rom.v Normal file
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@ -0,0 +1,44 @@
/*
(c) Raphaël Jacquot 2019
This file is part of hp_saturn.
hp_saturn is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
any later version.
hp_saturn is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with Foobar. If not, see <https://www.gnu.org/licenses/>.
*/
module saturn_hp48gx_rom (
i_clk,
i_reset,
i_bus_reset,
i_bus_clk_en,
i_bus_is_data,
o_bus_nibble_out,
i_bus_nibble_in
);
input wire [0:0] i_clk;
input wire [0:0] i_reset;
input wire [0:0] i_bus_reset;
input wire [0:0] i_bus_clk_en;
input wire [0:0] i_bus_is_data;
output reg [3:0] o_bus_nibble_out;
input wire [3:0] i_bus_nibble_in;
initial o_bus_nibble_out = 4'b0;
endmodule

49
saturn_top.v Normal file
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@ -0,0 +1,49 @@
/*
(c) Raphaël Jacquot 2019
This file is part of hp_saturn.
hp_saturn is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
any later version.
hp_saturn is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with Foobar. If not, see <https://www.gnu.org/licenses/>.
*/
`default_nettype none //
`ifdef SIM
module saturn_top;
saturn_bus main_bus (
.i_clk (clk),
.i_reset (reset),
.o_halt (halt)
);
reg [0:0] clk;
reg [0:0] reset;
wire [0:0] halt;
initial begin
$display("starting the simulation");
clk <= 0;
reset <= 1;
@(posedge clk);
@(posedge clk);
@(posedge clk);
reset <= 0;
@(posedge halt);
$finish;
end
endmodule
`endif

118
z_saturn_test.iv Executable file
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@ -0,0 +1,118 @@
#! /usr/bin/vvp -v
:ivl_version "11.0 (devel)" "(s20150603-597-gdc5429e5)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "system";
:vpi_module "vhdl_sys";
:vpi_module "vhdl_textio";
:vpi_module "v2005_math";
:vpi_module "va_math";
S_0x559e7ded19c0 .scope module, "saturn_top" "saturn_top" 2 24;
.timescale 0 0;
v0x559e7dee8e20_0 .var "clk", 0 0;
v0x559e7dee8ee0_0 .net "halt", 0 0, L_0x559e7debc610; 1 drivers
v0x559e7dee8fa0_0 .var "reset", 0 0;
E_0x559e7decc190 .event posedge, v0x559e7dee8c20_0;
E_0x559e7decc4b0 .event posedge, v0x559e7dee7370_0;
S_0x559e7ded1b50 .scope module, "main_bus" "saturn_bus" 2 26, 3 21 0, S_0x559e7ded19c0;
.timescale 0 0;
.port_info 0 /INPUT 1 "i_clk";
.port_info 1 /INPUT 1 "i_reset";
.port_info 2 /OUTPUT 1 "o_halt";
L_0x559e7debc610 .functor OR 1, v0x559e7dee8330_0, v0x559e7debc570_0, C4<0>, C4<0>;
v0x559e7dee8330_0 .var "bus_halt", 0 0;
v0x559e7dee8410_0 .net "ctrl_bus_clk_en", 0 0, v0x559e7dee7510_0; 1 drivers
v0x559e7dee8520_0 .net "ctrl_bus_is_data", 0 0, v0x559e7dee7640_0; 1 drivers
v0x559e7dee8610_0 .var "ctrl_bus_nibble_in", 3 0;
v0x559e7dee86d0_0 .net "ctrl_bus_nibble_out", 3 0, v0x559e7dee7720_0; 1 drivers
v0x559e7dee8810_0 .net "ctrl_bus_reset", 0 0, v0x559e7dee7800_0; 1 drivers
v0x559e7dee8920_0 .net "ctrl_halt", 0 0, v0x559e7debc570_0; 1 drivers
v0x559e7dee89e0_0 .net "i_clk", 0 0, v0x559e7dee8e20_0; 1 drivers
v0x559e7dee8ad0_0 .net "i_reset", 0 0, v0x559e7dee8fa0_0; 1 drivers
v0x559e7dee8c20_0 .net "o_halt", 0 0, L_0x559e7debc610; alias, 1 drivers
v0x559e7dee8d00_0 .net "rom_bus_nibble_out", 3 0, v0x559e7dee81b0_0; 1 drivers
E_0x559e7deccf00 .event edge, v0x559e7dee81b0_0;
S_0x559e7decf4f0 .scope module, "bus_controller" "saturn_bus_controller" 3 58, 4 21 0, S_0x559e7ded1b50;
.timescale 0 0;
.port_info 0 /INPUT 1 "i_clk";
.port_info 1 /INPUT 1 "i_reset";
.port_info 2 /OUTPUT 1 "o_bus_reset";
.port_info 3 /OUTPUT 1 "o_bus_clk_en";
.port_info 4 /OUTPUT 1 "o_bus_is_data";
.port_info 5 /OUTPUT 4 "o_bus_nibble_out";
.port_info 6 /INPUT 4 "i_bus_nibble_in";
.port_info 7 /OUTPUT 1 "o_halt";
v0x559e7debc570_0 .var "bus_error", 0 0;
v0x559e7debc730_0 .net "i_bus_nibble_in", 3 0, v0x559e7dee8610_0; 1 drivers
v0x559e7dee7370_0 .net "i_clk", 0 0, v0x559e7dee8e20_0; alias, 1 drivers
v0x559e7dee7430_0 .net "i_reset", 0 0, v0x559e7dee8fa0_0; alias, 1 drivers
v0x559e7dee7510_0 .var "o_bus_clk_en", 0 0;
v0x559e7dee7640_0 .var "o_bus_is_data", 0 0;
v0x559e7dee7720_0 .var "o_bus_nibble_out", 3 0;
v0x559e7dee7800_0 .var "o_bus_reset", 0 0;
v0x559e7dee78e0_0 .net "o_halt", 0 0, v0x559e7debc570_0; alias, 1 drivers
S_0x559e7dee7ac0 .scope module, "hp48gx_rom" "saturn_hp48gx_rom" 3 38, 5 21 0, S_0x559e7ded1b50;
.timescale 0 0;
.port_info 0 /INPUT 1 "i_clk";
.port_info 1 /INPUT 1 "i_reset";
.port_info 2 /INPUT 1 "i_bus_reset";
.port_info 3 /INPUT 1 "i_bus_clk_en";
.port_info 4 /INPUT 1 "i_bus_is_data";
.port_info 5 /OUTPUT 4 "o_bus_nibble_out";
.port_info 6 /INPUT 4 "i_bus_nibble_in";
v0x559e7dee7d20_0 .net "i_bus_clk_en", 0 0, v0x559e7dee7510_0; alias, 1 drivers
v0x559e7dee7de0_0 .net "i_bus_is_data", 0 0, v0x559e7dee7640_0; alias, 1 drivers
v0x559e7dee7e80_0 .net "i_bus_nibble_in", 3 0, v0x559e7dee7720_0; alias, 1 drivers
v0x559e7dee7f20_0 .net "i_bus_reset", 0 0, v0x559e7dee7800_0; alias, 1 drivers
v0x559e7dee7ff0_0 .net "i_clk", 0 0, v0x559e7dee8e20_0; alias, 1 drivers
v0x559e7dee80e0_0 .net "i_reset", 0 0, v0x559e7dee8fa0_0; alias, 1 drivers
v0x559e7dee81b0_0 .var "o_bus_nibble_out", 3 0;
.scope S_0x559e7dee7ac0;
T_0 ;
%pushi/vec4 0, 0, 4;
%store/vec4 v0x559e7dee81b0_0, 0, 4;
%end;
.thread T_0;
.scope S_0x559e7decf4f0;
T_1 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x559e7debc570_0, 0, 1;
%end;
.thread T_1;
.scope S_0x559e7ded1b50;
T_2 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x559e7dee8330_0, 0, 1;
%end;
.thread T_2;
.scope S_0x559e7ded1b50;
T_3 ;
%wait E_0x559e7deccf00;
%load/vec4 v0x559e7dee8d00_0;
%store/vec4 v0x559e7dee8610_0, 0, 4;
%jmp T_3;
.thread T_3, $push;
.scope S_0x559e7ded19c0;
T_4 ;
%vpi_call 2 37 "$display", "starting the simulation" {0 0 0};
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x559e7dee8e20_0, 0;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x559e7dee8fa0_0, 0;
%wait E_0x559e7decc4b0;
%wait E_0x559e7decc4b0;
%wait E_0x559e7decc4b0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x559e7dee8fa0_0, 0;
%wait E_0x559e7decc190;
%vpi_call 2 45 "$finish" {0 0 0};
%end;
.thread T_4;
# The file index is used to find the file name in the following table.
:file_names 6;
"N/A";
"<interactive>";
"saturn_top.v";
"saturn_bus.v";
"saturn_bus_controller.v";
"saturn_hp48gx_rom.v";