mirror of
https://github.com/sxpert/hp-saturn
synced 2024-12-26 09:58:09 +01:00
starts complete rewrite
This commit is contained in:
Raphael Jacquot
parent
570807cf61
commit
8866b8c175
8 changed files with 374 additions and 2 deletions
7
run.sh
7
run.sh
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@ -10,7 +10,10 @@
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# #exit
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# #exit
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# fi
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# fi
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#iverilog -v -Wall -DSIM -o mask_gen_tb mask_gen.v
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#iverilog -v -Wall -DSIM -o mask_gen_tb mask_gen.v
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iverilog -v -g2005-sv -gassertions -Wall -DSIM -o rom_tb saturn_core.v
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iverilog -v -Wall -DSIM -o z_saturn_test.iv -s saturn_top \
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saturn_top.v \
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saturn_bus.v saturn_hp48gx_rom.v \
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saturn_bus_controller.v
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IVERILOG_STATUS=$?
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IVERILOG_STATUS=$?
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#./mask_gen_tb
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#./mask_gen_tb
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echo "--------------------------------------------------------------------"
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echo "--------------------------------------------------------------------"
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@ -18,7 +21,7 @@ echo "IVERILOG_STATUS ${IVERILOG_STATUS}"
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echo "--------------------------------------------------------------------"
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echo "--------------------------------------------------------------------"
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if [ "${IVERILOG_STATUS}" = "0" ]
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if [ "${IVERILOG_STATUS}" = "0" ]
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then
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then
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./rom_tb
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./z_saturn_test.iv
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fi
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fi
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#vvp mask_gen_tb -lxt2
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#vvp mask_gen_tb -lxt2
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#gtkwave output.vcd
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#gtkwave output.vcd
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103
saturn_bus.v
Normal file
103
saturn_bus.v
Normal file
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@ -0,0 +1,103 @@
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/*
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(c) Raphaël Jacquot 2019
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This file is part of hp_saturn.
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hp_saturn is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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any later version.
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hp_saturn is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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||||||
|
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You should have received a copy of the GNU General Public License
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along with Foobar. If not, see <https://www.gnu.org/licenses/>.
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*/
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module saturn_bus (
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i_clk,
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i_reset,
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o_halt
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);
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input wire [0:0] i_clk;
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input wire [0:0] i_reset;
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output wire [0:0] o_halt;
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/**************************************************************************************************
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*
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* this is the main firmware rom module
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* this module is always active, there is no configuration.
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*
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*************************************************************************************************/
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saturn_hp48gx_rom hp48gx_rom (
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.i_clk (i_clk),
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.i_reset (i_reset),
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.i_bus_reset (ctrl_bus_reset),
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.i_bus_clk_en (ctrl_bus_clk_en),
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.i_bus_is_data (ctrl_bus_is_data),
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.o_bus_nibble_out (rom_bus_nibble_out),
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.i_bus_nibble_in (ctrl_bus_nibble_out)
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);
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wire [3:0] rom_bus_nibble_out;
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/**************************************************************************************************
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*
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* the main processor is hidden behind this bus controller device
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*
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*
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*************************************************************************************************/
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saturn_bus_controller bus_controller (
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.i_clk (i_clk),
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.i_reset (i_reset),
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.o_bus_reset (ctrl_bus_reset),
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.o_bus_clk_en (ctrl_bus_clk_en),
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.o_bus_is_data (ctrl_bus_is_data),
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.o_bus_nibble_out (ctrl_bus_nibble_out),
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.i_bus_nibble_in (ctrl_bus_nibble_in),
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// more ports should show up to allow for output to the serial port of debug information
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.o_halt (ctrl_halt)
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);
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wire [0:0] ctrl_bus_reset;
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wire [0:0] ctrl_bus_clk_en;
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wire [0:0] ctrl_bus_is_data;
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wire [3:0] ctrl_bus_nibble_out;
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reg [3:0] ctrl_bus_nibble_in;
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wire [0:0] ctrl_halt;
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/**************************************************************************************************
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*
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* priority logic for the bus
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*
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*
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*************************************************************************************************/
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reg bus_halt;
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initial bus_halt = 0;
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assign o_halt = bus_halt || ctrl_halt;
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/* handles modules priority
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* goes through all modules
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* if the module is active, this is the one giving out it's data
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* the last active module wins
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*/
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always @(*) begin
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ctrl_bus_nibble_in = rom_bus_nibble_out;
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end
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endmodule
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55
saturn_bus_controller.v
Normal file
55
saturn_bus_controller.v
Normal file
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@ -0,0 +1,55 @@
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/*
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(c) Raphaël Jacquot 2019
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This file is part of hp_saturn.
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hp_saturn is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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any later version.
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hp_saturn is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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||||||
|
|
||||||
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You should have received a copy of the GNU General Public License
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||||||
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along with Foobar. If not, see <https://www.gnu.org/licenses/>.
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*/
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module saturn_bus_controller (
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i_clk,
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i_reset,
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o_bus_reset,
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o_bus_clk_en,
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o_bus_is_data,
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o_bus_nibble_out,
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i_bus_nibble_in,
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o_halt
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);
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input wire [0:0] i_clk;
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input wire [0:0] i_reset;
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output reg [0:0] o_bus_reset;
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output reg [0:0] o_bus_clk_en;
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output reg [0:0] o_bus_is_data;
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output reg [3:0] o_bus_nibble_out;
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input wire [3:0] i_bus_nibble_in;
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output wire [0:0] o_halt;
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reg [0:0] bus_error;
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initial bus_error = 0;
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assign o_halt = bus_error;
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endmodule
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44
saturn_hp48gx_rom.v
Normal file
44
saturn_hp48gx_rom.v
Normal file
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@ -0,0 +1,44 @@
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/*
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(c) Raphaël Jacquot 2019
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This file is part of hp_saturn.
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hp_saturn is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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||||||
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any later version.
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hp_saturn is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
|
||||||
|
|
||||||
|
You should have received a copy of the GNU General Public License
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||||||
|
along with Foobar. If not, see <https://www.gnu.org/licenses/>.
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*/
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module saturn_hp48gx_rom (
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i_clk,
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i_reset,
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i_bus_reset,
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i_bus_clk_en,
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i_bus_is_data,
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o_bus_nibble_out,
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i_bus_nibble_in
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);
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input wire [0:0] i_clk;
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input wire [0:0] i_reset;
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input wire [0:0] i_bus_reset;
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input wire [0:0] i_bus_clk_en;
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input wire [0:0] i_bus_is_data;
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output reg [3:0] o_bus_nibble_out;
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input wire [3:0] i_bus_nibble_in;
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initial o_bus_nibble_out = 4'b0;
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endmodule
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49
saturn_top.v
Normal file
49
saturn_top.v
Normal file
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@ -0,0 +1,49 @@
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/*
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(c) Raphaël Jacquot 2019
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This file is part of hp_saturn.
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hp_saturn is free software: you can redistribute it and/or modify
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||||||
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it under the terms of the GNU General Public License as published by
|
||||||
|
the Free Software Foundation, either version 3 of the License, or
|
||||||
|
any later version.
|
||||||
|
|
||||||
|
hp_saturn is distributed in the hope that it will be useful,
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||||||
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but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
GNU General Public License for more details.
|
||||||
|
|
||||||
|
You should have received a copy of the GNU General Public License
|
||||||
|
along with Foobar. If not, see <https://www.gnu.org/licenses/>.
|
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*/
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`default_nettype none //
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`ifdef SIM
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module saturn_top;
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saturn_bus main_bus (
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.i_clk (clk),
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.i_reset (reset),
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.o_halt (halt)
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);
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reg [0:0] clk;
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reg [0:0] reset;
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wire [0:0] halt;
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initial begin
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$display("starting the simulation");
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clk <= 0;
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reset <= 1;
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@(posedge clk);
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@(posedge clk);
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@(posedge clk);
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reset <= 0;
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@(posedge halt);
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$finish;
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end
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endmodule
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`endif
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118
z_saturn_test.iv
Executable file
118
z_saturn_test.iv
Executable file
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@ -0,0 +1,118 @@
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#! /usr/bin/vvp -v
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:ivl_version "11.0 (devel)" "(s20150603-597-gdc5429e5)";
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:ivl_delay_selection "TYPICAL";
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:vpi_time_precision + 0;
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:vpi_module "system";
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:vpi_module "vhdl_sys";
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:vpi_module "vhdl_textio";
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:vpi_module "v2005_math";
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:vpi_module "va_math";
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S_0x559e7ded19c0 .scope module, "saturn_top" "saturn_top" 2 24;
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.timescale 0 0;
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v0x559e7dee8e20_0 .var "clk", 0 0;
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v0x559e7dee8ee0_0 .net "halt", 0 0, L_0x559e7debc610; 1 drivers
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v0x559e7dee8fa0_0 .var "reset", 0 0;
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E_0x559e7decc190 .event posedge, v0x559e7dee8c20_0;
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E_0x559e7decc4b0 .event posedge, v0x559e7dee7370_0;
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S_0x559e7ded1b50 .scope module, "main_bus" "saturn_bus" 2 26, 3 21 0, S_0x559e7ded19c0;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "i_clk";
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.port_info 1 /INPUT 1 "i_reset";
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.port_info 2 /OUTPUT 1 "o_halt";
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L_0x559e7debc610 .functor OR 1, v0x559e7dee8330_0, v0x559e7debc570_0, C4<0>, C4<0>;
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v0x559e7dee8330_0 .var "bus_halt", 0 0;
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v0x559e7dee8410_0 .net "ctrl_bus_clk_en", 0 0, v0x559e7dee7510_0; 1 drivers
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v0x559e7dee8520_0 .net "ctrl_bus_is_data", 0 0, v0x559e7dee7640_0; 1 drivers
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v0x559e7dee8610_0 .var "ctrl_bus_nibble_in", 3 0;
|
||||||
|
v0x559e7dee86d0_0 .net "ctrl_bus_nibble_out", 3 0, v0x559e7dee7720_0; 1 drivers
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||||||
|
v0x559e7dee8810_0 .net "ctrl_bus_reset", 0 0, v0x559e7dee7800_0; 1 drivers
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||||||
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v0x559e7dee8920_0 .net "ctrl_halt", 0 0, v0x559e7debc570_0; 1 drivers
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||||||
|
v0x559e7dee89e0_0 .net "i_clk", 0 0, v0x559e7dee8e20_0; 1 drivers
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||||||
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v0x559e7dee8ad0_0 .net "i_reset", 0 0, v0x559e7dee8fa0_0; 1 drivers
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||||||
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v0x559e7dee8c20_0 .net "o_halt", 0 0, L_0x559e7debc610; alias, 1 drivers
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||||||
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v0x559e7dee8d00_0 .net "rom_bus_nibble_out", 3 0, v0x559e7dee81b0_0; 1 drivers
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||||||
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E_0x559e7deccf00 .event edge, v0x559e7dee81b0_0;
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S_0x559e7decf4f0 .scope module, "bus_controller" "saturn_bus_controller" 3 58, 4 21 0, S_0x559e7ded1b50;
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|
.timescale 0 0;
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|
.port_info 0 /INPUT 1 "i_clk";
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||||||
|
.port_info 1 /INPUT 1 "i_reset";
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||||||
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.port_info 2 /OUTPUT 1 "o_bus_reset";
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||||||
|
.port_info 3 /OUTPUT 1 "o_bus_clk_en";
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||||||
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.port_info 4 /OUTPUT 1 "o_bus_is_data";
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.port_info 5 /OUTPUT 4 "o_bus_nibble_out";
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||||||
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.port_info 6 /INPUT 4 "i_bus_nibble_in";
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||||||
|
.port_info 7 /OUTPUT 1 "o_halt";
|
||||||
|
v0x559e7debc570_0 .var "bus_error", 0 0;
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||||||
|
v0x559e7debc730_0 .net "i_bus_nibble_in", 3 0, v0x559e7dee8610_0; 1 drivers
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v0x559e7dee7370_0 .net "i_clk", 0 0, v0x559e7dee8e20_0; alias, 1 drivers
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||||||
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v0x559e7dee7430_0 .net "i_reset", 0 0, v0x559e7dee8fa0_0; alias, 1 drivers
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||||||
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v0x559e7dee7510_0 .var "o_bus_clk_en", 0 0;
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v0x559e7dee7640_0 .var "o_bus_is_data", 0 0;
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v0x559e7dee7720_0 .var "o_bus_nibble_out", 3 0;
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v0x559e7dee7800_0 .var "o_bus_reset", 0 0;
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||||||
|
v0x559e7dee78e0_0 .net "o_halt", 0 0, v0x559e7debc570_0; alias, 1 drivers
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||||||
|
S_0x559e7dee7ac0 .scope module, "hp48gx_rom" "saturn_hp48gx_rom" 3 38, 5 21 0, S_0x559e7ded1b50;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "i_clk";
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.port_info 1 /INPUT 1 "i_reset";
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.port_info 2 /INPUT 1 "i_bus_reset";
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.port_info 3 /INPUT 1 "i_bus_clk_en";
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.port_info 4 /INPUT 1 "i_bus_is_data";
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.port_info 5 /OUTPUT 4 "o_bus_nibble_out";
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.port_info 6 /INPUT 4 "i_bus_nibble_in";
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v0x559e7dee7d20_0 .net "i_bus_clk_en", 0 0, v0x559e7dee7510_0; alias, 1 drivers
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||||||
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v0x559e7dee7de0_0 .net "i_bus_is_data", 0 0, v0x559e7dee7640_0; alias, 1 drivers
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||||||
|
v0x559e7dee7e80_0 .net "i_bus_nibble_in", 3 0, v0x559e7dee7720_0; alias, 1 drivers
|
||||||
|
v0x559e7dee7f20_0 .net "i_bus_reset", 0 0, v0x559e7dee7800_0; alias, 1 drivers
|
||||||
|
v0x559e7dee7ff0_0 .net "i_clk", 0 0, v0x559e7dee8e20_0; alias, 1 drivers
|
||||||
|
v0x559e7dee80e0_0 .net "i_reset", 0 0, v0x559e7dee8fa0_0; alias, 1 drivers
|
||||||
|
v0x559e7dee81b0_0 .var "o_bus_nibble_out", 3 0;
|
||||||
|
.scope S_0x559e7dee7ac0;
|
||||||
|
T_0 ;
|
||||||
|
%pushi/vec4 0, 0, 4;
|
||||||
|
%store/vec4 v0x559e7dee81b0_0, 0, 4;
|
||||||
|
%end;
|
||||||
|
.thread T_0;
|
||||||
|
.scope S_0x559e7decf4f0;
|
||||||
|
T_1 ;
|
||||||
|
%pushi/vec4 0, 0, 1;
|
||||||
|
%store/vec4 v0x559e7debc570_0, 0, 1;
|
||||||
|
%end;
|
||||||
|
.thread T_1;
|
||||||
|
.scope S_0x559e7ded1b50;
|
||||||
|
T_2 ;
|
||||||
|
%pushi/vec4 0, 0, 1;
|
||||||
|
%store/vec4 v0x559e7dee8330_0, 0, 1;
|
||||||
|
%end;
|
||||||
|
.thread T_2;
|
||||||
|
.scope S_0x559e7ded1b50;
|
||||||
|
T_3 ;
|
||||||
|
%wait E_0x559e7deccf00;
|
||||||
|
%load/vec4 v0x559e7dee8d00_0;
|
||||||
|
%store/vec4 v0x559e7dee8610_0, 0, 4;
|
||||||
|
%jmp T_3;
|
||||||
|
.thread T_3, $push;
|
||||||
|
.scope S_0x559e7ded19c0;
|
||||||
|
T_4 ;
|
||||||
|
%vpi_call 2 37 "$display", "starting the simulation" {0 0 0};
|
||||||
|
%pushi/vec4 0, 0, 1;
|
||||||
|
%assign/vec4 v0x559e7dee8e20_0, 0;
|
||||||
|
%pushi/vec4 1, 0, 1;
|
||||||
|
%assign/vec4 v0x559e7dee8fa0_0, 0;
|
||||||
|
%wait E_0x559e7decc4b0;
|
||||||
|
%wait E_0x559e7decc4b0;
|
||||||
|
%wait E_0x559e7decc4b0;
|
||||||
|
%pushi/vec4 0, 0, 1;
|
||||||
|
%assign/vec4 v0x559e7dee8fa0_0, 0;
|
||||||
|
%wait E_0x559e7decc190;
|
||||||
|
%vpi_call 2 45 "$finish" {0 0 0};
|
||||||
|
%end;
|
||||||
|
.thread T_4;
|
||||||
|
# The file index is used to find the file name in the following table.
|
||||||
|
:file_names 6;
|
||||||
|
"N/A";
|
||||||
|
"<interactive>";
|
||||||
|
"saturn_top.v";
|
||||||
|
"saturn_bus.v";
|
||||||
|
"saturn_bus_controller.v";
|
||||||
|
"saturn_hp48gx_rom.v";
|
||||||
Loading…
Reference in a new issue