Miroirs/hp-saturn
1
0
Fork 0
mirror of https://github.com/sxpert/hp-saturn synced 2024-12-24 21:59:33 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions

implement ST=[01] n

Browse source
This commit is contained in:
Raphael Jacquot 2019-02-04 17:00:08 +01:00
parent 610647d724
commit 7fcce53689
9 changed files with 33928 additions and 55 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

24
Makefile Normal file
View file

@ -0,0 +1,24 @@
PROJ=demo
CONSTR=versa.lpf
all: ${PROJ}.bit
pattern.vh: make_14seg.py text.in
python3 make_14seg.py < text.in > pattern.vh
%.json: %.v pattern.vh
yosys -p "synth_ecp5 -nomux -json $@" $<
%_out.config: %.json
nextpnr-ecp5 --json $< --lpf ${CONSTR} --basecfg ../../misc/basecfgs/empty_lfe5um5g-45f.config --textcfg $@ --um5g-45k --package CABGA381
%.bit: %_out.config
ecppack --svf-rowsize 100000 --svf ${PROJ}.svf $< $@
${PROJ}.svf: ${PROJ}.bit
prog: ${PROJ}.svf
openocd -f ../../misc/openocd/ecp5-versa5g.cfg -c "transport select jtag; init; svf $<; exit"
.PHONY: prog
.PRECIOUS: ${PROJ}.json ${PROJ}_out.config

124
gxrom-r-decompile Normal file
View file

@ -0,0 +1,124 @@
** hp48GX-R
000000 32 96 1b 80 ad fd 01 80 e5 f4 80 f6 08 60 16 02
000000 00000 23 P= 3 | 876cc
00002 69b1 GOTO 1b9 // #001bc | 876ce goto 87888
00006 08 CLRST
00008 da A=C A
0000a df CDEX A
0000c 100 R0=A w
0000f 85e ST=1 14 // set ST.14 interrupt pending
00012 4f0 GOC 0f // #00022 | 876de goc 876ee
00015 86f ?ST=0 f // | 876e1
00018 80 GOYES 08 // #00020 | 876e4 goyes 876ec
0001a 06 RSTK=C | 876e6
0001c 6120 GOTO 021 // #0003e | 876e8 goto 8770a
000010 30 78 5f 0f 02 00 00 00 00 00 00 00 82 16 18 31
00020 03 RTNCC | 876ec RTNCC
00022 87f ?ST=1 15 | 876ee ?ST=1 15
00025 5f GOYES f5 // #0001a | GOYES 876E6
00027 02 RTNSC
00029 00
0002b 00
0002d 00
0002f 00
00031 00
00033 00
00035 00
00037 0 28 61 81
000020 17 ef 11 00 51 0d f1 1f 01 10 f5 80 f0 80 f0 14
0003e 137 CD1EX
00041 1fe1100 D1=(5) 0011e
00048 15d0 DAT1=C 1
0004c 1ff1100 D1=(5) 0011f
00053 15f0 C=DAT1 1
00057 80f0 CPEX 0
0005b 80f4 CPEX 4
000030 53 e1 db 05 08 4f 08 0f 51 75 2d 08 3c 22 54 b0
0005f 135 D1=C
00062 1ebd50 D1=(4) 05db
00068 80f4 CPEX 4
0006c 80f0 CPEX 0
00070 1557 DAT1=C W
d2 80 c3 22 45 0b
000030 53 e1 db 05 08 4f 08 0f 51 75 2d 08 3c 22 54 b0
000040 60 12 8b 0e 24 80 23 05 0b 16 f7 41 15 47 70 41
000050 15 47 51 71 71 0f 19 54 71 a2 9f 51 75 71 af bf
000060 51 75 71 1f 81 51 75 71 0f 17 54 71 14 63 41 65
000070 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
000080 e8 00 f2 6f 40 00 69 0c 88 33 00 3a 24 11 10 81
000090 33 33 33 33 96 99 99 7e 33 33 33 73 b4 eb c1 01
0000a0 58 1d fb 12 00 51 0a 08 78 80 80 ec 1b 11 eb 10
0000b0 00 51 0a 03 1c c5 80 83 0c 47 16 b2 36 04 91 09
0000c0 03 14 c5 10 89 10 e5 80 80 0a 0f 58 70 62 21 61
0000d0 1c 10 0e 00 10 34 02 43 3f 5c 8a 2a 0b 72 d8 c6
001a0 c1 01 e0 00 01 43 20 34 f3 c5 a8 a2 b0 27
0000e0 1f 70 f9 11 cb 11 00 51 0e 08 a8 b2 80 80 28 51
001bc 8d6cf10 GOVLNG 01fc6
001c3 7 f9 11 bc 11 00 15 e0 80 8a 2b 08 08 82 15
0000f0 0c 91 1a 51 0e 08 a8 b1 80 80 18 51 0c e1 e1 00
000100 51 0f b1 0f 01 10 a5 90 20 06 16 f6 f8 1d 13 70
000110 c9 73 4b 84 7e a4 50 08 c8 06 0c e7 52 a7 69 e1
000120 08 06 51 77 fa 15 f7 51 77 fa 17 f7 51 77 01 18
000130 f7 41 07 16 47 41 17 43 e1 42 06 51 37 08 81 de
000140 ed 10 5e 60 10 74 a0 c1 1f 35 17 4c 41 07 16 4c
000150 41 87 22 6f 02 0b 46 04 50 12 0a 8e d0 12 be 5d
000160 10 75 17 ef 11 00 51 0f 31 05 87 e4 f0 02 b1 0e
000170 01 80 82 2d 2b c6 5e fd 03 1c c5 80 83 00 65 8e
000180 0d 25 70 91 2e 41 0e 26 d0 82 06 06 13 10 41 8c
000190 3e ad 80 80 1f c9 d1 12 c5 10 e9 30 80 51 0c 2d
0001a0 91 09 51 0c d8 b7 43 10 99 30 40 51 0c 91 2e 41
0001b0 0e 36 01 11 c4 91 38 51 0a 03 ba a0 51 0e 09 96
0001c0 0f 17 e9 12 c4 f8 a5 1b 80 af 9d 01 91 08 51 0e
0001d0 08 b8 90 19 e9 30 c0 51 0c 70 91 2e 41 0c 03 00
0001e0 02 b1 10 01 10 a5 80 80 36 00 08 48 12 85 80 80
0001f0 34 09 08 10 19 11 25 82 80 b4 29 08 80 80 1f c9
000200 10 e5 10 4e 65 10 d5 80 80 19 51 0c f8 1b 01 47
000210 7f 91 0d 0d 51 0a 08 48 d3 c6 c4 3a 74 48 00 2c
000220 31 14 25 13 8b 13 00 51 36 3b 12 89 13 25 93 23
000230 0f f8 1b 01 47 35 85 1e 4e 65 10 f5 10 c9 10 c5
000240 80 80 00 c2 12 bc 60 09 5e b0 04 2f 60 02 17 80
000250 80 86 0b 91 14 41 da 18 9e 51 10 f5 86 80 a6 12
000260 91 13 51 08 08 98 58 69 52 8a aa 40 02 c5 a5 7f
000270 08 28 31 81 4f 13 70 fa 9b 06 27 08 28 11 81 4f
000280 13 70 fa 9b 46 2d 52 8a 3a b0 e0 20 e5 20 a5 a8
000290 03 04 0e 1a ee 51 10 55 20 60 e4 9e e2 10 6b 56
0002a0 0a 6a 8e 80 b9 e1 19 05 51 6d 29 5e d2 fa f4 f4
0002b0 a4 a6 6a cc 14 9e 31 10 73 2c 31 d7 14 94 e1 19
0002c0 05 51 33 13 df e9 7e 90 82 53 e1 1e 05 51 0b 03
0002d0 03 0e 36 20 09 a6 13 29 11 a5 80 80 07 1b 08 28
000fd0 61 84 80 cc fa 01 07 b2 e8 49 fc d8 43 51 80 65
000fe0 86 00 f2 48 86 24 58 67 13 80 75 66 00 48 87 25
01fc0 68 00 2f
01fc6 846 ST=0 6
01fc9 842 ST=0 2
01fcc 857 ST=1 7
01fcf 6310 GOTO 013 => 01fe3
8 57 66 00 84 78 52
000ff0 58 86 c0 8f f4 08 8a cd 18 70 78 c6 83 d0 8f 39
01fe0 856
01fe3 80cf C=P f
8 4f 80 a8 dc 81 07 87 6c 38 0d f8 93
001000 07 88 18 12 9b 10 00 51 0e 08 b8 90 80 80 1a 08

17634
mask_gen.json Normal file
View file

File diff suppressed because it is too large Load diff

164
mask_gen.v Normal file
View file

@ -0,0 +1,164 @@
module mask_gen (
// ports
clk,
nibble_width,
nibble_start,
mask
);
input clk; // clock
input wire [3:0] nibble_width; // length of mask in nibbles
input wire [3:0] nibble_start; // nibble where the mask starts
output reg [63:0] mask;// 64 bits mask
reg [4:0] n_max;
wire [3:0] nm1 = n_max[3:0];
reg [15:0] bitmask_1;
reg [15:0] bitmask_2;
reg [15:0] bitmask;
//wire [3:0] nm1;
always @( posedge clk) begin
bitmask_1[ 0] = nibble_start==0;
bitmask_1[ 1] = nibble_start==1 | bitmask_1[0];
bitmask_1[ 2] = nibble_start==2 | bitmask_1[1];
bitmask_1[ 3] = nibble_start==3 | bitmask_1[2];
bitmask_1[ 4] = nibble_start==4 | bitmask_1[3];
bitmask_1[ 5] = nibble_start==5 | bitmask_1[4];
bitmask_1[ 6] = nibble_start==6 | bitmask_1[5];
bitmask_1[ 7] = nibble_start==7 | bitmask_1[6];
bitmask_1[ 8] = nibble_start==8 | bitmask_1[7];
bitmask_1[ 9] = nibble_start==9 | bitmask_1[8];
bitmask_1[10] = nibble_start==10 | bitmask_1[9];
bitmask_1[11] = nibble_start==11 | bitmask_1[10];
bitmask_1[12] = nibble_start==12 | bitmask_1[11];
bitmask_1[13] = nibble_start==13 | bitmask_1[12];
bitmask_1[14] = nibble_start==14 | bitmask_1[13];
bitmask_1[15] = nibble_start==15 | bitmask_1[14];
$display("bm1 : %b", bitmask_1);
n_max <= nibble_start + nibble_width + 1;
$display("n_max : %h", n_max);
//nm1[3:0] = n_max[3:0];
bitmask_2[15] = nm1==15;
bitmask_2[14] = nm1==14 | bitmask_2[15];
bitmask_2[13] = nm1==13 | bitmask_2[14];
bitmask_2[12] = nm1==12 | bitmask_2[13];
bitmask_2[11] = nm1==11 | bitmask_2[12];
bitmask_2[10] = nm1==10 | bitmask_2[11];
bitmask_2[ 9] = nm1==9 | bitmask_2[10];
bitmask_2[ 8] = nm1==8 | bitmask_2[9];
bitmask_2[ 7] = nm1==7 | bitmask_2[8];
bitmask_2[ 6] = nm1==6 | bitmask_2[7];
bitmask_2[ 5] = nm1==5 | bitmask_2[6];
bitmask_2[ 4] = nm1==4 | bitmask_2[5];
bitmask_2[ 3] = nm1==3 | bitmask_2[4];
bitmask_2[ 2] = nm1==2 | bitmask_2[3];
bitmask_2[ 1] = nm1==1 | bitmask_2[2];
bitmask_2[ 0] = nm1==0 | bitmask_2[1];
$display("bm2 : %b", bitmask_2);
bitmask = n_max[4] ? bitmask_1 | bitmask_2 : bitmask_1 & bitmask_2;
$display("bm : %b", bitmask);
mask[ 3: 0] = {4{bitmask[ 0]}};
mask[ 7: 4] = {4{bitmask[ 1]}};
mask[11: 8] = {4{bitmask[ 2]}};
mask[15:12] = {4{bitmask[ 3]}};
mask[19:16] = {4{bitmask[ 4]}};
mask[23:20] = {4{bitmask[ 5]}};
mask[27:24] = {4{bitmask[ 6]}};
mask[31:28] = {4{bitmask[ 7]}};
mask[35:32] = {4{bitmask[ 8]}};
mask[39:36] = {4{bitmask[ 9]}};
mask[43:40] = {4{bitmask[10]}};
mask[47:44] = {4{bitmask[11]}};
mask[51:48] = {4{bitmask[12]}};
mask[55:52] = {4{bitmask[13]}};
mask[59:56] = {4{bitmask[14]}};
mask[63:60] = {4{bitmask[15]}};
end
endmodule
`ifdef SIM
//`timescale 1 ns / 100 ps
module mask_gen_tb;
// inputs
reg clock;
reg [3:0] nw;
reg [3:0] ns;
// outputs
wire [63:0] m;
mask_gen U0 (
.clk (clock),
.nibble_width (nw),
.nibble_start (ns),
.mask (m)
);
always
#10 clock = (clock === 1'b0);
initial begin
//$monitor ("clk %b", clock);
$monitor ("clk %b | nw %d | ns %d | m %h", clock, nw, ns, m);
//#10 $display("1");
//#10 $display("2");
//#10 $finish;
end
initial begin
$dumpfile("text.vcd");
$dumpvars(clock, nw, ns, m);
$display($time, "starting simulation");
clock = 0;
$display("starting the simulation");
run_mask_gen(4, 0);
run_mask_gen(4, 1);
run_mask_gen(4, 2);
run_mask_gen(4, 3);
run_mask_gen(4, 4);
run_mask_gen(4, 5);
run_mask_gen(4, 6);
run_mask_gen(4, 7);
run_mask_gen(4, 8);
run_mask_gen(4, 9);
run_mask_gen(4,10);
run_mask_gen(4,11);
run_mask_gen(4,12);
run_mask_gen(4,13);
run_mask_gen(4,14);
run_mask_gen(4,15);
//run_mask_gen(4, 0);
//run_mask_gen(4, 0);
//run_mask_gen(4, 0);
//run_mask_gen(4, 0);
$finish;
end
task run_mask_gen;
input [3:0] _nw;
input [3:0] _ns;
begin
$display("running", _nw, _ns);
@(posedge clock);
nw = _nw;
ns = _ns;
end
endtask
endmodule
`endif

645
mask_gen_tb Executable file
View file

@ -0,0 +1,645 @@
#! /usr/bin/vvp -v
:ivl_version "10.1 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "system";
:vpi_module "vhdl_sys";
:vpi_module "v2005_math";
:vpi_module "va_math";
S_0x562a0b875c60 .scope module, "mask_gen_tb" "mask_gen_tb" 2 89;
.timescale 0 0;
v0x562a0b8968d0_0 .var "clock", 0 0;
v0x562a0b896990_0 .net "m", 63 0, v0x562a0b896040_0; 1 drivers
v0x562a0b896a60_0 .var "ns", 3 0;
v0x562a0b896b60_0 .var "nw", 3 0;
S_0x562a0b875de0 .scope module, "U0" "mask_gen" 2 100, 2 1 0, S_0x562a0b875c60;
.timescale 0 0;
.port_info 0 /INPUT 1 "clk"
.port_info 1 /INPUT 4 "nibble_width"
.port_info 2 /INPUT 4 "nibble_start"
.port_info 3 /OUTPUT 64 "mask"
v0x562a0b85f770_0 .var "bitmask", 15 0;
v0x562a0b895de0_0 .var "bitmask_1", 15 0;
v0x562a0b895ec0_0 .var "bitmask_2", 15 0;
v0x562a0b895f80_0 .net "clk", 0 0, v0x562a0b8968d0_0; 1 drivers
v0x562a0b896040_0 .var "mask", 63 0;
v0x562a0b896170_0 .var "n_max", 4 0;
v0x562a0b896250_0 .net "nibble_start", 3 0, v0x562a0b896a60_0; 1 drivers
v0x562a0b896330_0 .net "nibble_width", 3 0, v0x562a0b896b60_0; 1 drivers
v0x562a0b896410_0 .net "nm1", 3 0, L_0x562a0b896c30; 1 drivers
E_0x562a0b8468f0 .event posedge, v0x562a0b895f80_0;
L_0x562a0b896c30 .part v0x562a0b896170_0, 0, 4;
S_0x562a0b896570 .scope task, "run_mask_gen" "run_mask_gen" 2 151, 2 151 0, S_0x562a0b875c60;
.timescale 0 0;
v0x562a0b896710_0 .var "_ns", 3 0;
v0x562a0b8967f0_0 .var "_nw", 3 0;
TD_mask_gen_tb.run_mask_gen ;
%vpi_call 2 155 "$display", "running", v0x562a0b8967f0_0, v0x562a0b896710_0 {0 0 0};
%wait E_0x562a0b8468f0;
%load/vec4 v0x562a0b8967f0_0;
%store/vec4 v0x562a0b896b60_0, 0, 4;
%load/vec4 v0x562a0b896710_0;
%store/vec4 v0x562a0b896a60_0, 0, 4;
%end;
.scope S_0x562a0b875de0;
T_1 ;
%wait E_0x562a0b8468f0;
%load/vec4 v0x562a0b896250_0;
%pad/u 32;
%pushi/vec4 0, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%ix/load 4, 0, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895de0_0, 4, 1;
%load/vec4 v0x562a0b896250_0;
%pad/u 32;
%pushi/vec4 1, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895de0_0;
%parti/s 1, 0, 2;
%or;
%ix/load 4, 1, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895de0_0, 4, 1;
%load/vec4 v0x562a0b896250_0;
%pad/u 32;
%pushi/vec4 2, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895de0_0;
%parti/s 1, 1, 2;
%or;
%ix/load 4, 2, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895de0_0, 4, 1;
%load/vec4 v0x562a0b896250_0;
%pad/u 32;
%pushi/vec4 3, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895de0_0;
%parti/s 1, 2, 3;
%or;
%ix/load 4, 3, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895de0_0, 4, 1;
%load/vec4 v0x562a0b896250_0;
%pad/u 32;
%pushi/vec4 4, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895de0_0;
%parti/s 1, 3, 3;
%or;
%ix/load 4, 4, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895de0_0, 4, 1;
%load/vec4 v0x562a0b896250_0;
%pad/u 32;
%pushi/vec4 5, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895de0_0;
%parti/s 1, 4, 4;
%or;
%ix/load 4, 5, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895de0_0, 4, 1;
%load/vec4 v0x562a0b896250_0;
%pad/u 32;
%pushi/vec4 6, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895de0_0;
%parti/s 1, 5, 4;
%or;
%ix/load 4, 6, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895de0_0, 4, 1;
%load/vec4 v0x562a0b896250_0;
%pad/u 32;
%pushi/vec4 7, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895de0_0;
%parti/s 1, 6, 4;
%or;
%ix/load 4, 7, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895de0_0, 4, 1;
%load/vec4 v0x562a0b896250_0;
%pad/u 32;
%pushi/vec4 8, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895de0_0;
%parti/s 1, 7, 4;
%or;
%ix/load 4, 8, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895de0_0, 4, 1;
%load/vec4 v0x562a0b896250_0;
%pad/u 32;
%pushi/vec4 9, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895de0_0;
%parti/s 1, 8, 5;
%or;
%ix/load 4, 9, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895de0_0, 4, 1;
%load/vec4 v0x562a0b896250_0;
%pad/u 32;
%pushi/vec4 10, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895de0_0;
%parti/s 1, 9, 5;
%or;
%ix/load 4, 10, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895de0_0, 4, 1;
%load/vec4 v0x562a0b896250_0;
%pad/u 32;
%pushi/vec4 11, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895de0_0;
%parti/s 1, 10, 5;
%or;
%ix/load 4, 11, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895de0_0, 4, 1;
%load/vec4 v0x562a0b896250_0;
%pad/u 32;
%pushi/vec4 12, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895de0_0;
%parti/s 1, 11, 5;
%or;
%ix/load 4, 12, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895de0_0, 4, 1;
%load/vec4 v0x562a0b896250_0;
%pad/u 32;
%pushi/vec4 13, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895de0_0;
%parti/s 1, 12, 5;
%or;
%ix/load 4, 13, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895de0_0, 4, 1;
%load/vec4 v0x562a0b896250_0;
%pad/u 32;
%pushi/vec4 14, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895de0_0;
%parti/s 1, 13, 5;
%or;
%ix/load 4, 14, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895de0_0, 4, 1;
%load/vec4 v0x562a0b896250_0;
%pad/u 32;
%pushi/vec4 15, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895de0_0;
%parti/s 1, 14, 5;
%or;
%ix/load 4, 15, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895de0_0, 4, 1;
%vpi_call 2 37 "$display", "bm1 : %b", v0x562a0b895de0_0 {0 0 0};
%load/vec4 v0x562a0b896250_0;
%pad/u 5;
%load/vec4 v0x562a0b896330_0;
%pad/u 5;
%add;
%addi 1, 0, 5;
%assign/vec4 v0x562a0b896170_0, 0;
%vpi_call 2 41 "$display", "n_max : %h", v0x562a0b896170_0 {0 0 0};
%load/vec4 v0x562a0b896410_0;
%pad/u 32;
%pushi/vec4 15, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%ix/load 4, 15, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895ec0_0, 4, 1;
%load/vec4 v0x562a0b896410_0;
%pad/u 32;
%pushi/vec4 14, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895ec0_0;
%parti/s 1, 15, 5;
%or;
%ix/load 4, 14, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895ec0_0, 4, 1;
%load/vec4 v0x562a0b896410_0;
%pad/u 32;
%pushi/vec4 13, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895ec0_0;
%parti/s 1, 14, 5;
%or;
%ix/load 4, 13, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895ec0_0, 4, 1;
%load/vec4 v0x562a0b896410_0;
%pad/u 32;
%pushi/vec4 12, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895ec0_0;
%parti/s 1, 13, 5;
%or;
%ix/load 4, 12, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895ec0_0, 4, 1;
%load/vec4 v0x562a0b896410_0;
%pad/u 32;
%pushi/vec4 11, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895ec0_0;
%parti/s 1, 12, 5;
%or;
%ix/load 4, 11, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895ec0_0, 4, 1;
%load/vec4 v0x562a0b896410_0;
%pad/u 32;
%pushi/vec4 10, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895ec0_0;
%parti/s 1, 11, 5;
%or;
%ix/load 4, 10, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895ec0_0, 4, 1;
%load/vec4 v0x562a0b896410_0;
%pad/u 32;
%pushi/vec4 9, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895ec0_0;
%parti/s 1, 10, 5;
%or;
%ix/load 4, 9, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895ec0_0, 4, 1;
%load/vec4 v0x562a0b896410_0;
%pad/u 32;
%pushi/vec4 8, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895ec0_0;
%parti/s 1, 9, 5;
%or;
%ix/load 4, 8, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895ec0_0, 4, 1;
%load/vec4 v0x562a0b896410_0;
%pad/u 32;
%pushi/vec4 7, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895ec0_0;
%parti/s 1, 8, 5;
%or;
%ix/load 4, 7, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895ec0_0, 4, 1;
%load/vec4 v0x562a0b896410_0;
%pad/u 32;
%pushi/vec4 6, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895ec0_0;
%parti/s 1, 7, 4;
%or;
%ix/load 4, 6, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895ec0_0, 4, 1;
%load/vec4 v0x562a0b896410_0;
%pad/u 32;
%pushi/vec4 5, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895ec0_0;
%parti/s 1, 6, 4;
%or;
%ix/load 4, 5, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895ec0_0, 4, 1;
%load/vec4 v0x562a0b896410_0;
%pad/u 32;
%pushi/vec4 4, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895ec0_0;
%parti/s 1, 5, 4;
%or;
%ix/load 4, 4, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895ec0_0, 4, 1;
%load/vec4 v0x562a0b896410_0;
%pad/u 32;
%pushi/vec4 3, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895ec0_0;
%parti/s 1, 4, 4;
%or;
%ix/load 4, 3, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895ec0_0, 4, 1;
%load/vec4 v0x562a0b896410_0;
%pad/u 32;
%pushi/vec4 2, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895ec0_0;
%parti/s 1, 3, 3;
%or;
%ix/load 4, 2, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895ec0_0, 4, 1;
%load/vec4 v0x562a0b896410_0;
%pad/u 32;
%pushi/vec4 1, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895ec0_0;
%parti/s 1, 2, 3;
%or;
%ix/load 4, 1, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895ec0_0, 4, 1;
%load/vec4 v0x562a0b896410_0;
%pad/u 32;
%pushi/vec4 0, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x562a0b895ec0_0;
%parti/s 1, 1, 2;
%or;
%ix/load 4, 0, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b895ec0_0, 4, 1;
%vpi_call 2 60 "$display", "bm2 : %b", v0x562a0b895ec0_0 {0 0 0};
%load/vec4 v0x562a0b896170_0;
%parti/s 1, 4, 4;
%flag_set/vec4 8;
%jmp/0 T_1.0, 8;
%load/vec4 v0x562a0b895de0_0;
%load/vec4 v0x562a0b895ec0_0;
%or;
%jmp/1 T_1.1, 8;
T_1.0 ; End of true expr.
%load/vec4 v0x562a0b895de0_0;
%load/vec4 v0x562a0b895ec0_0;
%and;
%jmp/0 T_1.1, 8;
; End of false expr.
%blend;
T_1.1;
%store/vec4 v0x562a0b85f770_0, 0, 16;
%vpi_call 2 63 "$display", "bm : %b", v0x562a0b85f770_0 {0 0 0};
%load/vec4 v0x562a0b85f770_0;
%parti/s 1, 0, 2;
%replicate 4;
%ix/load 4, 0, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b896040_0, 4, 4;
%load/vec4 v0x562a0b85f770_0;
%parti/s 1, 1, 2;
%replicate 4;
%ix/load 4, 4, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b896040_0, 4, 4;
%load/vec4 v0x562a0b85f770_0;
%parti/s 1, 2, 3;
%replicate 4;
%ix/load 4, 8, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b896040_0, 4, 4;
%load/vec4 v0x562a0b85f770_0;
%parti/s 1, 3, 3;
%replicate 4;
%ix/load 4, 12, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b896040_0, 4, 4;
%load/vec4 v0x562a0b85f770_0;
%parti/s 1, 4, 4;
%replicate 4;
%ix/load 4, 16, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b896040_0, 4, 4;
%load/vec4 v0x562a0b85f770_0;
%parti/s 1, 5, 4;
%replicate 4;
%ix/load 4, 20, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b896040_0, 4, 4;
%load/vec4 v0x562a0b85f770_0;
%parti/s 1, 6, 4;
%replicate 4;
%ix/load 4, 24, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b896040_0, 4, 4;
%load/vec4 v0x562a0b85f770_0;
%parti/s 1, 7, 4;
%replicate 4;
%ix/load 4, 28, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b896040_0, 4, 4;
%load/vec4 v0x562a0b85f770_0;
%parti/s 1, 8, 5;
%replicate 4;
%ix/load 4, 32, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b896040_0, 4, 4;
%load/vec4 v0x562a0b85f770_0;
%parti/s 1, 9, 5;
%replicate 4;
%ix/load 4, 36, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b896040_0, 4, 4;
%load/vec4 v0x562a0b85f770_0;
%parti/s 1, 10, 5;
%replicate 4;
%ix/load 4, 40, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b896040_0, 4, 4;
%load/vec4 v0x562a0b85f770_0;
%parti/s 1, 11, 5;
%replicate 4;
%ix/load 4, 44, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b896040_0, 4, 4;
%load/vec4 v0x562a0b85f770_0;
%parti/s 1, 12, 5;
%replicate 4;
%ix/load 4, 48, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b896040_0, 4, 4;
%load/vec4 v0x562a0b85f770_0;
%parti/s 1, 13, 5;
%replicate 4;
%ix/load 4, 52, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b896040_0, 4, 4;
%load/vec4 v0x562a0b85f770_0;
%parti/s 1, 14, 5;
%replicate 4;
%ix/load 4, 56, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b896040_0, 4, 4;
%load/vec4 v0x562a0b85f770_0;
%parti/s 1, 15, 5;
%replicate 4;
%ix/load 4, 60, 0;
%flag_set/imm 4, 0;
%store/vec4 v0x562a0b896040_0, 4, 4;
%jmp T_1;
.thread T_1;
.scope S_0x562a0b875c60;
T_2 ;
%delay 10, 0;
%load/vec4 v0x562a0b8968d0_0;
%pushi/vec4 0, 0, 1;
%cmp/e;
%flag_get/vec4 6;
%store/vec4 v0x562a0b8968d0_0, 0, 1;
%jmp T_2;
.thread T_2;
.scope S_0x562a0b875c60;
T_3 ;
%vpi_call 2 113 "$monitor", "clk %b | nw %d | ns %d | m %h", v0x562a0b8968d0_0, v0x562a0b896b60_0, v0x562a0b896a60_0, v0x562a0b896990_0 {0 0 0};
%end;
.thread T_3;
.scope S_0x562a0b875c60;
T_4 ;
%vpi_call 2 121 "$dumpfile", "text.vcd" {0 0 0};
%vpi_call 2 122 "$dumpvars", v0x562a0b8968d0_0, v0x562a0b896b60_0, v0x562a0b896a60_0, v0x562a0b896990_0 {0 0 0};
%vpi_call 2 123 "$display", $time, "starting simulation" {0 0 0};
%pushi/vec4 0, 0, 1;
%store/vec4 v0x562a0b8968d0_0, 0, 1;
%vpi_call 2 125 "$display", "starting the simulation" {0 0 0};
%pushi/vec4 4, 0, 4;
%store/vec4 v0x562a0b8967f0_0, 0, 4;
%pushi/vec4 0, 0, 4;
%store/vec4 v0x562a0b896710_0, 0, 4;
%fork TD_mask_gen_tb.run_mask_gen, S_0x562a0b896570;
%join;
%pushi/vec4 4, 0, 4;
%store/vec4 v0x562a0b8967f0_0, 0, 4;
%pushi/vec4 1, 0, 4;
%store/vec4 v0x562a0b896710_0, 0, 4;
%fork TD_mask_gen_tb.run_mask_gen, S_0x562a0b896570;
%join;
%pushi/vec4 4, 0, 4;
%store/vec4 v0x562a0b8967f0_0, 0, 4;
%pushi/vec4 2, 0, 4;
%store/vec4 v0x562a0b896710_0, 0, 4;
%fork TD_mask_gen_tb.run_mask_gen, S_0x562a0b896570;
%join;
%pushi/vec4 4, 0, 4;
%store/vec4 v0x562a0b8967f0_0, 0, 4;
%pushi/vec4 3, 0, 4;
%store/vec4 v0x562a0b896710_0, 0, 4;
%fork TD_mask_gen_tb.run_mask_gen, S_0x562a0b896570;
%join;
%pushi/vec4 4, 0, 4;
%store/vec4 v0x562a0b8967f0_0, 0, 4;
%pushi/vec4 4, 0, 4;
%store/vec4 v0x562a0b896710_0, 0, 4;
%fork TD_mask_gen_tb.run_mask_gen, S_0x562a0b896570;
%join;
%pushi/vec4 4, 0, 4;
%store/vec4 v0x562a0b8967f0_0, 0, 4;
%pushi/vec4 5, 0, 4;
%store/vec4 v0x562a0b896710_0, 0, 4;
%fork TD_mask_gen_tb.run_mask_gen, S_0x562a0b896570;
%join;
%pushi/vec4 4, 0, 4;
%store/vec4 v0x562a0b8967f0_0, 0, 4;
%pushi/vec4 6, 0, 4;
%store/vec4 v0x562a0b896710_0, 0, 4;
%fork TD_mask_gen_tb.run_mask_gen, S_0x562a0b896570;
%join;
%pushi/vec4 4, 0, 4;
%store/vec4 v0x562a0b8967f0_0, 0, 4;
%pushi/vec4 7, 0, 4;
%store/vec4 v0x562a0b896710_0, 0, 4;
%fork TD_mask_gen_tb.run_mask_gen, S_0x562a0b896570;
%join;
%pushi/vec4 4, 0, 4;
%store/vec4 v0x562a0b8967f0_0, 0, 4;
%pushi/vec4 8, 0, 4;
%store/vec4 v0x562a0b896710_0, 0, 4;
%fork TD_mask_gen_tb.run_mask_gen, S_0x562a0b896570;
%join;
%pushi/vec4 4, 0, 4;
%store/vec4 v0x562a0b8967f0_0, 0, 4;
%pushi/vec4 9, 0, 4;
%store/vec4 v0x562a0b896710_0, 0, 4;
%fork TD_mask_gen_tb.run_mask_gen, S_0x562a0b896570;
%join;
%pushi/vec4 4, 0, 4;
%store/vec4 v0x562a0b8967f0_0, 0, 4;
%pushi/vec4 10, 0, 4;
%store/vec4 v0x562a0b896710_0, 0, 4;
%fork TD_mask_gen_tb.run_mask_gen, S_0x562a0b896570;
%join;
%pushi/vec4 4, 0, 4;
%store/vec4 v0x562a0b8967f0_0, 0, 4;
%pushi/vec4 11, 0, 4;
%store/vec4 v0x562a0b896710_0, 0, 4;
%fork TD_mask_gen_tb.run_mask_gen, S_0x562a0b896570;
%join;
%pushi/vec4 4, 0, 4;
%store/vec4 v0x562a0b8967f0_0, 0, 4;
%pushi/vec4 12, 0, 4;
%store/vec4 v0x562a0b896710_0, 0, 4;
%fork TD_mask_gen_tb.run_mask_gen, S_0x562a0b896570;
%join;
%pushi/vec4 4, 0, 4;
%store/vec4 v0x562a0b8967f0_0, 0, 4;
%pushi/vec4 13, 0, 4;
%store/vec4 v0x562a0b896710_0, 0, 4;
%fork TD_mask_gen_tb.run_mask_gen, S_0x562a0b896570;
%join;
%pushi/vec4 4, 0, 4;
%store/vec4 v0x562a0b8967f0_0, 0, 4;
%pushi/vec4 14, 0, 4;
%store/vec4 v0x562a0b896710_0, 0, 4;
%fork TD_mask_gen_tb.run_mask_gen, S_0x562a0b896570;
%join;
%pushi/vec4 4, 0, 4;
%store/vec4 v0x562a0b8967f0_0, 0, 4;
%pushi/vec4 15, 0, 4;
%store/vec4 v0x562a0b896710_0, 0, 4;
%fork TD_mask_gen_tb.run_mask_gen, S_0x562a0b896570;
%join;
%vpi_call 2 147 "$finish" {0 0 0};
%end;
.thread T_4;
# The file index is used to find the file name in the following table.
:file_names 3;
"N/A";
"<interactive>";
"mask_gen.v";

845
rom_tb Executable file
View file

@ -0,0 +1,845 @@
#! /usr/bin/vvp -v
:ivl_version "10.1 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "system";
:vpi_module "vhdl_sys";
:vpi_module "v2005_math";
:vpi_module "va_math";
S_0x564b714feed0 .scope module, "rom_tb" "rom_tb" 2 903;
.timescale 0 0;
v0x564b71520e20_0 .var "clk", 0 0;
v0x564b71520ee0_0 .net "decstate", 31 0, v0x564b71520040_0; 1 drivers
v0x564b71520fa0_0 .net "halt", 0 0, v0x564b71520100_0; 1 drivers
v0x564b715210a0_0 .var "reset", 0 0;
v0x564b71521170_0 .net "runstate", 3 0, v0x564b71520b90_0; 1 drivers
E_0x564b71481d20 .event posedge, v0x564b71520100_0;
S_0x564b714ff050 .scope module, "saturn" "saturn_core" 2 910, 2 39 0, S_0x564b714feed0;
.timescale 0 0;
.port_info 0 /INPUT 1 "clk"
.port_info 1 /INPUT 1 "reset"
.port_info 2 /OUTPUT 1 "halt"
.port_info 3 /OUTPUT 4 "runstate"
.port_info 4 /OUTPUT 32 "decstate"
P_0x564b714ff1d0 .param/l "DEC" 1 2 96, +C4<00000000000000000000000000000001>;
P_0x564b714ff210 .param/l "DECODE_0" 1 2 59, C4<00000000000000000000000000000001>;
P_0x564b714ff250 .param/l "DECODE_0X" 1 2 60, C4<00000000000000000000000000000010>;
P_0x564b714ff290 .param/l "DECODE_1" 1 2 62, C4<00000000000000000000000000010000>;
P_0x564b714ff2d0 .param/l "DECODE_14" 1 2 64, C4<00000000000000000000010000010000>;
P_0x564b714ff310 .param/l "DECODE_15" 1 2 65, C4<00000000000000000000010100010000>;
P_0x564b714ff350 .param/l "DECODE_1X" 1 2 63, C4<00000000000000000000000000010001>;
P_0x564b714ff390 .param/l "DECODE_8" 1 2 76, C4<00000000000000000000000010000000>;
P_0x564b714ff3d0 .param/l "DECODE_80" 1 2 78, C4<00000000000000000000000010000010>;
P_0x564b714ff410 .param/l "DECODE_82" 1 2 84, C4<00000000000000000000001010000000>;
P_0x564b714ff450 .param/l "DECODE_8X" 1 2 77, C4<00000000000000000000000010000001>;
P_0x564b714ff490 .param/l "DECODE_A" 1 2 92, C4<00000000000000000000000010100000>;
P_0x564b714ff4d0 .param/l "DECODE_A_FS" 1 2 93, C4<00000000000000000000000010100001>;
P_0x564b714ff510 .param/l "DECODE_C_EQ_P_N" 1 2 82, C4<00000000000000001100000010000000>;
P_0x564b714ff550 .param/l "DECODE_D0_EQ_5N" 1 2 67, C4<00000000000000000000101100010000>;
P_0x564b714ff590 .param/l "DECODE_GOSBVL" 1 2 90, C4<00000000000000000000111110000000>;
P_0x564b714ff5d0 .param/l "DECODE_GOTO" 1 2 74, C4<00000000000000000000000001100000>;
P_0x564b714ff610 .param/l "DECODE_GOVLNG" 1 2 89, C4<00000000000000000000110110000000>;
P_0x564b714ff650 .param/l "DECODE_LC" 1 2 72, C4<00000000000000000000000000110001>;
P_0x564b714ff690 .param/l "DECODE_LC_LEN" 1 2 71, C4<00000000000000000000000000110000>;
P_0x564b714ff6d0 .param/l "DECODE_MEMACCESS" 1 2 66, C4<00000000000000000000010000010001>;
P_0x564b714ff710 .param/l "DECODE_P_EQ" 1 2 69, C4<00000000000000000000000000100000>;
P_0x564b714ff750 .param/l "DECODE_RESET" 1 2 80, C4<00000000000000001010000010000000>;
P_0x564b714ff790 .param/l "DECODE_START" 1 2 57, C4<00000000000000000000000000000000>;
P_0x564b714ff7d0 .param/l "DECODE_ST_EQ_0_N" 1 2 86, C4<00000000000000000000010010000000>;
P_0x564b714ff810 .param/l "DECODE_ST_EQ_1_N" 1 2 87, C4<00000000000000000000010110000000>;
P_0x564b714ff850 .param/l "HEX" 1 2 95, +C4<00000000000000000000000000000000>;
P_0x564b714ff890 .param/l "READ_ROM_CLK" 1 2 49, +C4<00000000000000000000000000000010>;
P_0x564b714ff8d0 .param/l "READ_ROM_STA" 1 2 48, +C4<00000000000000000000000000000001>;
P_0x564b714ff910 .param/l "READ_ROM_STR" 1 2 50, +C4<00000000000000000000000000000011>;
P_0x564b714ff950 .param/l "READ_ROM_VAL" 1 2 51, +C4<00000000000000000000000000000100>;
P_0x564b714ff990 .param/l "RUN_DECODE" 1 2 53, +C4<00000000000000000000000000001111>;
P_0x564b714ff9d0 .param/l "RUN_EXEC" 1 2 52, +C4<00000000000000000000000000001110>;
P_0x564b714ffa10 .param/l "RUN_START" 1 2 47, +C4<00000000000000000000000000000000>;
v0x564b714f9f80_0 .var "A", 63 0;
v0x564b714fd0f0_0 .var "B", 63 0;
v0x564b7151f260_0 .var "C", 63 0;
v0x564b7151f350_0 .var "Carry", 0 0;
v0x564b7151f410_0 .var "D", 63 0;
v0x564b7151f540_0 .var "D0", 19 0;
v0x564b7151f620_0 .var "D1", 19 0;
v0x564b7151f700_0 .var "HST", 3 0;
v0x564b7151f7e0_0 .var "P", 3 0;
v0x564b7151f8c0_0 .var "PC", 19 0;
v0x564b7151f9a0_0 .var "R0", 63 0;
v0x564b7151fa80_0 .var "R1", 63 0;
v0x564b7151fb60_0 .var "R2", 63 0;
v0x564b7151fc40_0 .var "R3", 63 0;
v0x564b7151fd20_0 .var "R4", 63 0;
v0x564b7151fe00 .array "RSTK", 7 0, 19 0;
v0x564b7151fec0_0 .var "ST", 15 0;
v0x564b7151ffa0_0 .net "clk", 0 0, v0x564b71520e20_0; 1 drivers
v0x564b71520040_0 .var "decstate", 31 0;
v0x564b71520100_0 .var "halt", 0 0;
v0x564b715201c0_0 .var "hex_dec", 0 0;
v0x564b71520280_0 .var "jump_base", 19 0;
v0x564b71520360_0 .var "jump_offset", 19 0;
v0x564b71520440_0 .var "load_cnt", 3 0;
v0x564b71520520_0 .var "load_ctr", 3 0;
v0x564b71520600_0 .var "nibble", 3 0;
v0x564b715206e0_0 .net "reset", 0 0, v0x564b715210a0_0; 1 drivers
v0x564b715207a0_0 .var "rom_address", 19 0;
v0x564b71520890_0 .var "rom_clock", 0 0;
v0x564b71520930_0 .var "rom_enable", 0 0;
v0x564b71520a00_0 .net "rom_nibble", 3 0, v0x564b714f6780_0; 1 drivers
v0x564b71520ad0_0 .var "rstk_ptr", 2 0;
v0x564b71520b90_0 .var "runstate", 3 0;
v0x564b71520c70_0 .var "saved_PC", 19 0;
S_0x564b714ffa60 .scope module, "calc_rom" "hp_rom" 2 141, 2 9 0, S_0x564b714ff050;
.timescale 0 0;
.port_info 0 /INPUT 1 "clk"
.port_info 1 /INPUT 20 "address"
.port_info 2 /INPUT 1 "enable"
.port_info 3 /OUTPUT 4 "nibble_out"
P_0x564b714b9680 .param/str "ROM_FILENAME" 1 2 15, "rom-gx-r.hex";
v0x564b714f1070_0 .net "address", 19 0, v0x564b715207a0_0; 1 drivers
v0x564b714f2910_0 .net "clk", 0 0, v0x564b71520e20_0; alias, 1 drivers
v0x564b714f4190_0 .net "enable", 0 0, v0x564b71520930_0; 1 drivers
v0x564b714f6780_0 .var "nibble_out", 3 0;
v0x564b714f8550 .array "rom", 1048575 0, 3 0;
E_0x564b714b6ba0 .event posedge, v0x564b714f2910_0;
.scope S_0x564b714ffa60;
T_0 ;
%vpi_call 2 23 "$readmemh", P_0x564b714b9680, v0x564b714f8550 {0 0 0};
%end;
.thread T_0;
.scope S_0x564b714ffa60;
T_1 ;
%wait E_0x564b714b6ba0;
%load/vec4 v0x564b714f4190_0;
%flag_set/vec4 8;
%jmp/0xz T_1.0, 8;
%load/vec4 v0x564b714f1070_0;
%pad/u 22;
%ix/vec4 4;
%load/vec4a v0x564b714f8550, 4;
%assign/vec4 v0x564b714f6780_0, 0;
T_1.0 ;
%jmp T_1;
.thread T_1;
.scope S_0x564b714ff050;
T_2 ;
%wait E_0x564b714b6ba0;
%load/vec4 v0x564b715206e0_0;
%flag_set/vec4 8;
%jmp/0xz T_2.0, 8;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x564b715201c0_0, 0;
%pushi/vec4 7, 0, 3;
%assign/vec4 v0x564b71520ad0_0, 0;
%pushi/vec4 0, 0, 20;
%assign/vec4 v0x564b7151f8c0_0, 0;
%pushi/vec4 0, 0, 4;
%assign/vec4 v0x564b7151f7e0_0, 0;
%pushi/vec4 0, 0, 16;
%assign/vec4 v0x564b7151fec0_0, 0;
%pushi/vec4 0, 0, 4;
%assign/vec4 v0x564b7151f700_0, 0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x564b7151f350_0, 0;
%pushi/vec4 0, 0, 20;
%ix/load 3, 0, 0;
%flag_set/imm 4, 0;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0x564b7151fe00, 0, 4;
%pushi/vec4 0, 0, 20;
%ix/load 3, 1, 0;
%flag_set/imm 4, 0;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0x564b7151fe00, 0, 4;
%pushi/vec4 0, 0, 20;
%ix/load 3, 2, 0;
%flag_set/imm 4, 0;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0x564b7151fe00, 0, 4;
%pushi/vec4 0, 0, 20;
%ix/load 3, 3, 0;
%flag_set/imm 4, 0;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0x564b7151fe00, 0, 4;
%pushi/vec4 0, 0, 20;
%ix/load 3, 4, 0;
%flag_set/imm 4, 0;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0x564b7151fe00, 0, 4;
%pushi/vec4 0, 0, 20;
%ix/load 3, 5, 0;
%flag_set/imm 4, 0;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0x564b7151fe00, 0, 4;
%pushi/vec4 0, 0, 20;
%ix/load 3, 6, 0;
%flag_set/imm 4, 0;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0x564b7151fe00, 0, 4;
%pushi/vec4 0, 0, 20;
%ix/load 3, 7, 0;
%flag_set/imm 4, 0;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0x564b7151fe00, 0, 4;
%pushi/vec4 0, 0, 20;
%assign/vec4 v0x564b7151f540_0, 0;
%pushi/vec4 0, 0, 20;
%assign/vec4 v0x564b7151f620_0, 0;
%pushi/vec4 0, 0, 64;
%assign/vec4 v0x564b714f9f80_0, 0;
%pushi/vec4 0, 0, 64;
%assign/vec4 v0x564b714fd0f0_0, 0;
%pushi/vec4 0, 0, 64;
%assign/vec4 v0x564b7151f260_0, 0;
%pushi/vec4 0, 0, 64;
%assign/vec4 v0x564b7151f410_0, 0;
%pushi/vec4 0, 0, 64;
%assign/vec4 v0x564b7151f9a0_0, 0;
%pushi/vec4 0, 0, 64;
%assign/vec4 v0x564b7151fa80_0, 0;
%pushi/vec4 0, 0, 64;
%assign/vec4 v0x564b7151fb60_0, 0;
%pushi/vec4 0, 0, 64;
%assign/vec4 v0x564b7151fc40_0, 0;
%pushi/vec4 0, 0, 64;
%assign/vec4 v0x564b7151fd20_0, 0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x564b71520100_0, 0;
%pushi/vec4 0, 0, 4;
%assign/vec4 v0x564b71520b90_0, 0;
%pushi/vec4 0, 0, 32;
%assign/vec4 v0x564b71520040_0, 0;
%jmp T_2.1;
T_2.0 ;
%load/vec4 v0x564b71520b90_0;
%pad/u 32;
%cmpi/e 0, 0, 32;
%jmp/0xz T_2.2, 4;
%pushi/vec4 1, 0, 4;
%assign/vec4 v0x564b71520b90_0, 0;
T_2.2 ;
T_2.1 ;
%jmp T_2;
.thread T_2;
.scope S_0x564b714ff050;
T_3 ;
%wait E_0x564b714b6ba0;
%load/vec4 v0x564b71520b90_0;
%pad/u 32;
%pushi/vec4 0, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x564b715206e0_0;
%inv;
%and;
%flag_set/vec4 8;
%jmp/0xz T_3.0, 8;
%load/vec4 v0x564b7151f8c0_0;
%assign/vec4 v0x564b71520c70_0, 0;
%load/vec4 v0x564b715201c0_0;
%flag_set/vec4 8;
%jmp/0 T_3.2, 8;
%pushi/vec4 4474179, 0, 24; draw_string_vec4
%jmp/1 T_3.3, 8;
T_3.2 ; End of true expr.
%pushi/vec4 4736344, 0, 24; draw_string_vec4
%jmp/0 T_3.3, 8;
; End of false expr.
%blend;
T_3.3;
%vpi_call 2 202 "$display", "PC: %05h Carry: %b h: %s rp: %h RSTK7: %05h", v0x564b7151f8c0_0, v0x564b7151f350_0, S<0,vec4,u24>, v0x564b71520ad0_0, &A<v0x564b7151fe00, 7> {1 0 0};
%vpi_call 2 203 "$display", "P: %h HST: %b ST: %b RSTK6: %5h", v0x564b7151f7e0_0, v0x564b7151f700_0, v0x564b7151fec0_0, &A<v0x564b7151fe00, 6> {0 0 0};
%vpi_call 2 204 "$display", "A: %h R0: %h RSTK5: %5h", v0x564b714f9f80_0, v0x564b7151f9a0_0, &A<v0x564b7151fe00, 5> {0 0 0};
%vpi_call 2 205 "$display", "B: %h R1: %h RSTK4: %5h", v0x564b714fd0f0_0, v0x564b7151fa80_0, &A<v0x564b7151fe00, 4> {0 0 0};
%vpi_call 2 206 "$display", "C: %h R2: %h RSTK3: %5h", v0x564b7151f260_0, v0x564b7151fb60_0, &A<v0x564b7151fe00, 3> {0 0 0};
%vpi_call 2 207 "$display", "D: %h R3: %h RSTK2: %5h", v0x564b7151f410_0, v0x564b7151fc40_0, &A<v0x564b7151fe00, 2> {0 0 0};
%vpi_call 2 208 "$display", "D0: %h D1: %h R4: %h RSTK1: %5h", v0x564b7151f540_0, v0x564b7151f620_0, v0x564b7151fd20_0, &A<v0x564b7151fe00, 1> {0 0 0};
%vpi_call 2 209 "$display", " RSTK0: %5h", &A<v0x564b7151fe00, 0> {0 0 0};
T_3.0 ;
%jmp T_3;
.thread T_3;
.scope S_0x564b714ff050;
T_4 ;
%wait E_0x564b714b6ba0;
%load/vec4 v0x564b71520b90_0;
%pad/u 32;
%cmpi/e 1, 0, 32;
%jmp/0xz T_4.0, 4;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x564b71520930_0, 0;
%load/vec4 v0x564b7151f8c0_0;
%assign/vec4 v0x564b715207a0_0, 0;
%pushi/vec4 2, 0, 4;
%assign/vec4 v0x564b71520b90_0, 0;
T_4.0 ;
%jmp T_4;
.thread T_4;
.scope S_0x564b714ff050;
T_5 ;
%wait E_0x564b714b6ba0;
%load/vec4 v0x564b71520b90_0;
%pad/u 32;
%cmpi/e 2, 0, 32;
%jmp/0xz T_5.0, 4;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x564b71520890_0, 0;
%pushi/vec4 3, 0, 4;
%assign/vec4 v0x564b71520b90_0, 0;
T_5.0 ;
%jmp T_5;
.thread T_5;
.scope S_0x564b714ff050;
T_6 ;
%wait E_0x564b714b6ba0;
%load/vec4 v0x564b71520b90_0;
%pad/u 32;
%cmpi/e 3, 0, 32;
%jmp/0xz T_6.0, 4;
%load/vec4 v0x564b71520a00_0;
%assign/vec4 v0x564b71520600_0, 0;
%load/vec4 v0x564b7151f8c0_0;
%addi 1, 0, 20;
%assign/vec4 v0x564b7151f8c0_0, 0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x564b71520930_0, 0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x564b71520890_0, 0;
%pushi/vec4 4, 0, 4;
%assign/vec4 v0x564b71520b90_0, 0;
T_6.0 ;
%jmp T_6;
.thread T_6;
.scope S_0x564b714ff050;
T_7 ;
%wait E_0x564b714b6ba0;
%load/vec4 v0x564b71520b90_0;
%pad/u 32;
%pushi/vec4 4, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x564b71520040_0;
%pushi/vec4 0, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%and;
%flag_set/vec4 8;
%jmp/0xz T_7.0, 8;
%pushi/vec4 15, 0, 4;
%assign/vec4 v0x564b71520b90_0, 0;
%load/vec4 v0x564b71520600_0;
%dup/vec4;
%pushi/vec4 2, 0, 4;
%cmp/u;
%jmp/1 T_7.2, 6;
%dup/vec4;
%pushi/vec4 6, 0, 4;
%cmp/u;
%jmp/1 T_7.3, 6;
%dup/vec4;
%pushi/vec4 8, 0, 4;
%cmp/u;
%jmp/1 T_7.4, 6;
%vpi_call 2 276 "$display", "%05h nibble %h => unimplemented", v0x564b71520c70_0, v0x564b71520600_0 {0 0 0};
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x564b71520100_0, 0;
%jmp T_7.6;
T_7.2 ;
%pushi/vec4 32, 0, 32;
%assign/vec4 v0x564b71520040_0, 0;
%jmp T_7.6;
T_7.3 ;
%pushi/vec4 96, 0, 32;
%assign/vec4 v0x564b71520040_0, 0;
%jmp T_7.6;
T_7.4 ;
%pushi/vec4 128, 0, 32;
%assign/vec4 v0x564b71520040_0, 0;
%jmp T_7.6;
T_7.6 ;
%pop/vec4 1;
T_7.0 ;
%jmp T_7;
.thread T_7;
.scope S_0x564b714ff050;
T_8 ;
%wait E_0x564b714b6ba0;
%load/vec4 v0x564b71520040_0;
%cmpi/e 32, 0, 32;
%jmp/0xz T_8.0, 4;
%load/vec4 v0x564b71520b90_0;
%dup/vec4;
%pushi/vec4 15, 0, 4;
%cmp/u;
%jmp/1 T_8.2, 6;
%dup/vec4;
%pushi/vec4 1, 0, 4;
%cmp/u;
%jmp/1 T_8.3, 6;
%dup/vec4;
%pushi/vec4 2, 0, 4;
%cmp/u;
%jmp/1 T_8.4, 6;
%dup/vec4;
%pushi/vec4 3, 0, 4;
%cmp/u;
%jmp/1 T_8.5, 6;
%dup/vec4;
%pushi/vec4 4, 0, 4;
%cmp/u;
%jmp/1 T_8.6, 6;
%vpi_call 2 470 "$display", "runstate %h", v0x564b71520b90_0 {0 0 0};
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x564b71520100_0, 0;
%jmp T_8.8;
T_8.2 ;
%pushi/vec4 1, 0, 4;
%assign/vec4 v0x564b71520b90_0, 0;
%jmp T_8.8;
T_8.3 ;
%jmp T_8.8;
T_8.4 ;
%jmp T_8.8;
T_8.5 ;
%jmp T_8.8;
T_8.6 ;
%load/vec4 v0x564b71520600_0;
%assign/vec4 v0x564b7151f7e0_0, 0;
%vpi_call 2 462 "$display", "%05h P=\011%h", v0x564b71520c70_0, v0x564b71520600_0 {0 0 0};
%pushi/vec4 0, 0, 4;
%assign/vec4 v0x564b71520b90_0, 0;
%pushi/vec4 0, 0, 32;
%assign/vec4 v0x564b71520040_0, 0;
%jmp T_8.8;
T_8.8 ;
%pop/vec4 1;
T_8.0 ;
%jmp T_8;
.thread T_8;
.scope S_0x564b714ff050;
T_9 ;
%wait E_0x564b714b6ba0;
%load/vec4 v0x564b71520040_0;
%cmpi/e 96, 0, 32;
%jmp/0xz T_9.0, 4;
%load/vec4 v0x564b71520b90_0;
%dup/vec4;
%pushi/vec4 15, 0, 4;
%cmp/u;
%jmp/1 T_9.2, 6;
%dup/vec4;
%pushi/vec4 1, 0, 4;
%cmp/u;
%jmp/1 T_9.3, 6;
%dup/vec4;
%pushi/vec4 2, 0, 4;
%cmp/u;
%jmp/1 T_9.4, 6;
%dup/vec4;
%pushi/vec4 3, 0, 4;
%cmp/u;
%jmp/1 T_9.5, 6;
%dup/vec4;
%pushi/vec4 4, 0, 4;
%cmp/u;
%jmp/1 T_9.6, 6;
%dup/vec4;
%pushi/vec4 14, 0, 4;
%cmp/u;
%jmp/1 T_9.7, 6;
%vpi_call 2 562 "$display", "runstate %h", v0x564b71520b90_0 {0 0 0};
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x564b71520100_0, 0;
%jmp T_9.9;
T_9.2 ;
%pushi/vec4 1, 0, 4;
%assign/vec4 v0x564b71520b90_0, 0;
%load/vec4 v0x564b7151f8c0_0;
%assign/vec4 v0x564b71520280_0, 0;
%pushi/vec4 0, 0, 20;
%assign/vec4 v0x564b71520360_0, 0;
%pushi/vec4 2, 0, 4;
%assign/vec4 v0x564b71520440_0, 0;
%pushi/vec4 0, 0, 4;
%assign/vec4 v0x564b71520520_0, 0;
%vpi_call 2 534 "$write", "%5h GOTO\011", v0x564b71520c70_0 {0 0 0};
%jmp T_9.9;
T_9.3 ;
%jmp T_9.9;
T_9.4 ;
%jmp T_9.9;
T_9.5 ;
%jmp T_9.9;
T_9.6 ;
%load/vec4 v0x564b71520600_0;
%ix/load 5, 0, 0;
%load/vec4 v0x564b71520520_0;
%pad/u 32;
%muli 4, 0, 32;
%ix/vec4 4;
%assign/vec4/off/d v0x564b71520360_0, 4, 5;
%vpi_call 2 542 "$write", "%1h", v0x564b71520600_0 {0 0 0};
%load/vec4 v0x564b71520520_0;
%load/vec4 v0x564b71520440_0;
%cmp/e;
%jmp/0xz T_9.10, 4;
%pushi/vec4 14, 0, 4;
%assign/vec4 v0x564b71520b90_0, 0;
%jmp T_9.11;
T_9.10 ;
%load/vec4 v0x564b71520520_0;
%addi 1, 0, 4;
%assign/vec4 v0x564b71520520_0, 0;
%pushi/vec4 1, 0, 4;
%assign/vec4 v0x564b71520b90_0, 0;
T_9.11 ;
%jmp T_9.9;
T_9.7 ;
%load/vec4 v0x564b71520280_0;
%load/vec4 v0x564b71520360_0;
%add;
%vpi_call 2 554 "$display", "\011=> %05h", S<0,vec4,u20> {1 0 0};
%load/vec4 v0x564b71520280_0;
%load/vec4 v0x564b71520360_0;
%add;
%assign/vec4 v0x564b7151f8c0_0, 0;
%pushi/vec4 0, 0, 4;
%assign/vec4 v0x564b71520b90_0, 0;
%pushi/vec4 0, 0, 32;
%assign/vec4 v0x564b71520040_0, 0;
%jmp T_9.9;
T_9.9 ;
%pop/vec4 1;
T_9.0 ;
%jmp T_9;
.thread T_9;
.scope S_0x564b714ff050;
T_10 ;
%wait E_0x564b714b6ba0;
%load/vec4 v0x564b71520040_0;
%cmpi/e 128, 0, 32;
%jmp/0xz T_10.0, 4;
%load/vec4 v0x564b71520b90_0;
%dup/vec4;
%pushi/vec4 15, 0, 4;
%cmp/u;
%jmp/1 T_10.2, 6;
%dup/vec4;
%pushi/vec4 1, 0, 4;
%cmp/u;
%jmp/1 T_10.3, 6;
%dup/vec4;
%pushi/vec4 2, 0, 4;
%cmp/u;
%jmp/1 T_10.4, 6;
%dup/vec4;
%pushi/vec4 3, 0, 4;
%cmp/u;
%jmp/1 T_10.5, 6;
%dup/vec4;
%pushi/vec4 4, 0, 4;
%cmp/u;
%jmp/1 T_10.6, 6;
%vpi_call 2 601 "$display", "runstate %h", v0x564b71520b90_0 {0 0 0};
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x564b71520100_0, 0;
%jmp T_10.8;
T_10.2 ;
%pushi/vec4 1, 0, 4;
%assign/vec4 v0x564b71520b90_0, 0;
%jmp T_10.8;
T_10.3 ;
%jmp T_10.8;
T_10.4 ;
%jmp T_10.8;
T_10.5 ;
%jmp T_10.8;
T_10.6 ;
%load/vec4 v0x564b71520600_0;
%dup/vec4;
%pushi/vec4 4, 0, 4;
%cmp/u;
%jmp/1 T_10.9, 6;
%dup/vec4;
%pushi/vec4 5, 0, 4;
%cmp/u;
%jmp/1 T_10.10, 6;
%dup/vec4;
%pushi/vec4 13, 0, 4;
%cmp/u;
%jmp/1 T_10.11, 6;
%vpi_call 2 591 "$display", "unhandled instruction prefix 8%h", v0x564b71520600_0 {0 0 0};
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x564b71520100_0, 0;
%jmp T_10.13;
T_10.9 ;
%pushi/vec4 1152, 0, 32;
%assign/vec4 v0x564b71520040_0, 0;
%jmp T_10.13;
T_10.10 ;
%pushi/vec4 1408, 0, 32;
%assign/vec4 v0x564b71520040_0, 0;
%jmp T_10.13;
T_10.11 ;
%pushi/vec4 3456, 0, 32;
%assign/vec4 v0x564b71520040_0, 0;
%jmp T_10.13;
T_10.13 ;
%pop/vec4 1;
%pushi/vec4 15, 0, 4;
%assign/vec4 v0x564b71520b90_0, 0;
%jmp T_10.8;
T_10.8 ;
%pop/vec4 1;
T_10.0 ;
%jmp T_10;
.thread T_10;
.scope S_0x564b714ff050;
T_11 ;
%wait E_0x564b714b6ba0;
%load/vec4 v0x564b71520040_0;
%pushi/vec4 1152, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x564b71520040_0;
%pushi/vec4 1408, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%or;
%flag_set/vec4 8;
%jmp/0xz T_11.0, 8;
%load/vec4 v0x564b71520b90_0;
%dup/vec4;
%pushi/vec4 15, 0, 4;
%cmp/u;
%jmp/1 T_11.2, 6;
%dup/vec4;
%pushi/vec4 1, 0, 4;
%cmp/u;
%jmp/1 T_11.3, 6;
%dup/vec4;
%pushi/vec4 2, 0, 4;
%cmp/u;
%jmp/1 T_11.4, 6;
%dup/vec4;
%pushi/vec4 3, 0, 4;
%cmp/u;
%jmp/1 T_11.5, 6;
%dup/vec4;
%pushi/vec4 4, 0, 4;
%cmp/u;
%jmp/1 T_11.6, 6;
%vpi_call 2 726 "$display", "decstate %h", v0x564b71520040_0 {0 0 0};
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x564b71520100_0, 0;
%jmp T_11.8;
T_11.2 ;
%pushi/vec4 1, 0, 4;
%assign/vec4 v0x564b71520b90_0, 0;
%jmp T_11.8;
T_11.3 ;
%jmp T_11.8;
T_11.4 ;
%jmp T_11.8;
T_11.5 ;
%jmp T_11.8;
T_11.6 ;
%load/vec4 v0x564b71520040_0;
%dup/vec4;
%pushi/vec4 1152, 0, 32;
%cmp/u;
%jmp/1 T_11.9, 6;
%dup/vec4;
%pushi/vec4 1408, 0, 32;
%cmp/u;
%jmp/1 T_11.10, 6;
%jmp T_11.11;
T_11.9 ;
%vpi_call 2 708 "$display", "%05h ST=0\011%h", v0x564b71520c70_0, v0x564b71520600_0 {0 0 0};
%pushi/vec4 0, 0, 1;
%ix/load 5, 0, 0;
%ix/getv 4, v0x564b71520600_0;
%assign/vec4/off/d v0x564b7151fec0_0, 4, 5;
%jmp T_11.11;
T_11.10 ;
%vpi_call 2 715 "$display", "%05h ST=1\011%h", v0x564b71520c70_0, v0x564b71520600_0 {0 0 0};
%pushi/vec4 1, 0, 1;
%ix/load 5, 0, 0;
%ix/getv 4, v0x564b71520600_0;
%assign/vec4/off/d v0x564b7151fec0_0, 4, 5;
%jmp T_11.11;
T_11.11 ;
%pop/vec4 1;
%pushi/vec4 0, 0, 4;
%assign/vec4 v0x564b71520b90_0, 0;
%pushi/vec4 0, 0, 32;
%assign/vec4 v0x564b71520040_0, 0;
%jmp T_11.8;
T_11.8 ;
%pop/vec4 1;
T_11.0 ;
%jmp T_11;
.thread T_11;
.scope S_0x564b714ff050;
T_12 ;
%wait E_0x564b714b6ba0;
%load/vec4 v0x564b71520040_0;
%pushi/vec4 3456, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%load/vec4 v0x564b71520040_0;
%pushi/vec4 3968, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%or;
%flag_set/vec4 8;
%jmp/0xz T_12.0, 8;
%load/vec4 v0x564b71520b90_0;
%dup/vec4;
%pushi/vec4 15, 0, 4;
%cmp/u;
%jmp/1 T_12.2, 6;
%dup/vec4;
%pushi/vec4 1, 0, 4;
%cmp/u;
%jmp/1 T_12.3, 6;
%dup/vec4;
%pushi/vec4 2, 0, 4;
%cmp/u;
%jmp/1 T_12.4, 6;
%dup/vec4;
%pushi/vec4 3, 0, 4;
%cmp/u;
%jmp/1 T_12.5, 6;
%dup/vec4;
%pushi/vec4 4, 0, 4;
%cmp/u;
%jmp/1 T_12.6, 6;
%dup/vec4;
%pushi/vec4 14, 0, 4;
%cmp/u;
%jmp/1 T_12.7, 6;
%vpi_call 2 828 "$display", "decstate %h", v0x564b71520040_0 {0 0 0};
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x564b71520100_0, 0;
%jmp T_12.9;
T_12.2 ;
%pushi/vec4 0, 0, 20;
%assign/vec4 v0x564b71520280_0, 0;
%pushi/vec4 4, 0, 4;
%assign/vec4 v0x564b71520440_0, 0;
%pushi/vec4 0, 0, 4;
%assign/vec4 v0x564b71520520_0, 0;
%load/vec4 v0x564b71520040_0;
%dup/vec4;
%pushi/vec4 3456, 0, 32;
%cmp/u;
%jmp/1 T_12.10, 6;
%dup/vec4;
%pushi/vec4 3968, 0, 32;
%cmp/u;
%jmp/1 T_12.11, 6;
%jmp T_12.12;
T_12.10 ;
%vpi_call 2 791 "$write", "%5h GOVLNG\011", v0x564b71520c70_0 {0 0 0};
%jmp T_12.12;
T_12.11 ;
%vpi_call 2 792 "$write", "%5h GOSBVL\011", v0x564b71520c70_0 {0 0 0};
%jmp T_12.12;
T_12.12 ;
%pop/vec4 1;
%load/vec4 v0x564b71520040_0;
%cmpi/e 3968, 0, 32;
%jmp/0xz T_12.13, 4;
%load/vec4 v0x564b71520ad0_0;
%addi 1, 0, 3;
%assign/vec4 v0x564b71520ad0_0, 0;
T_12.13 ;
%pushi/vec4 1, 0, 4;
%assign/vec4 v0x564b71520b90_0, 0;
%jmp T_12.9;
T_12.3 ;
%jmp T_12.9;
T_12.4 ;
%jmp T_12.9;
T_12.5 ;
%jmp T_12.9;
T_12.6 ;
%load/vec4 v0x564b71520600_0;
%load/vec4 v0x564b71520520_0;
%pad/u 32;
%muli 4, 0, 32;
%ix/vec4 4;
%store/vec4 v0x564b71520280_0, 4, 4;
%vpi_call 2 805 "$write", "%1h", v0x564b71520600_0 {0 0 0};
%load/vec4 v0x564b71520520_0;
%load/vec4 v0x564b71520440_0;
%cmp/e;
%jmp/0xz T_12.15, 4;
%pushi/vec4 14, 0, 4;
%assign/vec4 v0x564b71520b90_0, 0;
%jmp T_12.16;
T_12.15 ;
%load/vec4 v0x564b71520520_0;
%addi 1, 0, 4;
%assign/vec4 v0x564b71520520_0, 0;
%pushi/vec4 1, 0, 4;
%assign/vec4 v0x564b71520b90_0, 0;
T_12.16 ;
%jmp T_12.9;
T_12.7 ;
%vpi_call 2 817 "$display", "\011=> %5h", v0x564b71520280_0 {0 0 0};
%load/vec4 v0x564b71520040_0;
%cmpi/e 3968, 0, 32;
%jmp/0xz T_12.17, 4;
%load/vec4 v0x564b7151f8c0_0;
%load/vec4 v0x564b71520ad0_0;
%pad/u 5;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0x564b7151fe00, 0, 4;
T_12.17 ;
%load/vec4 v0x564b71520280_0;
%assign/vec4 v0x564b7151f8c0_0, 0;
%pushi/vec4 0, 0, 4;
%assign/vec4 v0x564b71520b90_0, 0;
%pushi/vec4 0, 0, 32;
%assign/vec4 v0x564b71520040_0, 0;
%jmp T_12.9;
T_12.9 ;
%pop/vec4 1;
T_12.0 ;
%jmp T_12;
.thread T_12;
.scope S_0x564b714feed0;
T_13 ;
%delay 10, 0;
%load/vec4 v0x564b71520e20_0;
%pushi/vec4 0, 0, 1;
%cmp/e;
%flag_get/vec4 6;
%store/vec4 v0x564b71520e20_0, 0, 1;
%jmp T_13;
.thread T_13;
.scope S_0x564b714feed0;
T_14 ;
%end;
.thread T_14;
.scope S_0x564b714feed0;
T_15 ;
%vpi_call 2 926 "$display", "starting the simulation" {0 0 0};
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x564b71520e20_0, 0;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x564b715210a0_0, 0;
%wait E_0x564b714b6ba0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x564b715210a0_0, 0;
%wait E_0x564b71481d20;
%vpi_call 2 932 "$finish" {0 0 0};
%end;
.thread T_15;
# The file index is used to find the file name in the following table.
:file_names 3;
"N/A";
"<interactive>";
"saturn_core.v";

14385
saturn_core.json Normal file
View file

File diff suppressed because it is too large Load diff

89
saturn_core.v
View file

@ -581,8 +581,8 @@ always @(posedge clk)
case (nibble) case (nibble)
//4'h0: decode_80(); //4'h0: decode_80();
//4'h2: decode_82(); //4'h2: decode_82();
//4'h4: inst_st_eq_0_n(); 4'h4: decstate <= DECODE_ST_EQ_0_N;
//4'h5: inst_st_eq_1_n(); 4'h5: decstate <= DECODE_ST_EQ_1_N;
4'hd: decstate <= DECODE_GOVLNG; 4'hd: decstate <= DECODE_GOVLNG;
//4'hf: decstate <= DECODE_GOSBVL; //4'hf: decstate <= DECODE_GOSBVL;
default: default:
@ -690,65 +690,44 @@ endtask
*/ */
/****************************************************************************** /******************************************************************************
* ---------- field ----------- * 84n ST=0 n
* A B fs d * 85n ST=1 n
* ----------------------------
* 140 148 150a 158x DAT0=A field
* 141 149 151a 159x DAT1=A field
* 142 14A 152a 15Ax A=DAT0 field
* 143 14B 153a 15Bx A=DAT1 field
* 144 14C 154a 15Cx DAT0=C field
* 145 14D 155a 15Dx DAT1=C field
* 146 14E 156a 15Ex C=DAT0 field
* 147 14F 157a 15Fx C=DAT1 field
*
* fs: P WP XS X S M B W
* a: 0 1 2 3 4 5 6 7
*
* x = d - 1 x = n - 1
*/ */
always @(posedge clk)
if ((decstate == DECODE_ST_EQ_0_N) | (decstate == DECODE_ST_EQ_1_N))
/* case (runstate)
// 84n ST=0 n RUN_DECODE: runstate <= READ_ROM_STA;
task inst_st_eq_0_n; READ_ROM_STA, READ_ROM_CLK, READ_ROM_STR: ;
case (decstate ) READ_ROM_VAL:
DECODE_8X:
begin
decstate <= DECODE_ST_EQ_0_N;
read_state <= READ_START;
end
DECODE_ST_EQ_0_N:
if (read_state != READ_VALID) read_rom();
else
begin begin
$display("%05h ST=0\t%h", saved_PC, nibble); case (decstate)
ST[nibble] <= 0; DECODE_ST_EQ_0_N:
end_decode(); begin
`ifdef SIM
$display("%05h ST=0\t%h", saved_PC, nibble);
`endif
ST[nibble] <= 0;
end
DECODE_ST_EQ_1_N:
begin
`ifdef SIM
$display("%05h ST=1\t%h", saved_PC, nibble);
`endif
ST[nibble] <= 1;
end
endcase
runstate <= RUN_START;
decstate <= DECODE_START;
end end
endcase default:
endtask
// 85n ST=1 n
task inst_st_eq_1_n;
case (decstate )
DECODE_8X:
begin
decstate <= DECODE_ST_EQ_1_N;
read_state <= READ_START;
end
DECODE_ST_EQ_1_N:
if (read_state != READ_VALID) read_rom();
else
begin begin
$display("%05h ST=1\t%h", saved_PC, nibble); `ifdef SIM
ST[nibble] <= 1; $display("decstate %h", decstate);
end_decode(); `endif
halt <= 1;
end end
endcase endcase
endtask
*/
/****************************************************************************** /******************************************************************************
* 8Dzyxwv GOVLNG vwxyz * 8Dzyxwv GOVLNG vwxyz

73
text.vcd Normal file
View file

@ -0,0 +1,73 @@
$date
Thu Jan 31 14:59:26 2019
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module mask_gen_tb $end
$var reg 4 ! nw [3:0] $end
$upscope $end
$scope module mask_gen_tb $end
$var reg 4 " ns [3:0] $end
$upscope $end
$scope module mask_gen_tb $end
$var wire 64 # m [63:0] $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
bx #
bx "
bx !
$end
#10
b0 "
b100 !
#30
b111111111111111111110000 #
b1 "
#50
b1111111111111111111100000000 #
b10 "
#70
b11111111111111111111000000000000 #
b11 "
#90
b111111111111111111110000000000000000 #
b100 "
#110
b1111111111111111111100000000000000000000 #
b101 "
#130
b11111111111111111111000000000000000000000000 #
b110 "
#150
b111111111111111111110000000000000000000000000000 #
b111 "
#170
b1111111111111111111100000000000000000000000000000000 #
b1000 "
#190
b11111111111111111111000000000000000000000000000000000000 #
b1001 "
#210
b111111111111111111110000000000000000000000000000000000000000 #
b1010 "
#230
b1111111111111111111100000000000000000000000000000000000000000000 #
b1011 "
#250
b1111111111111111000000000000000000000000000000000000000000001111 #
b1100 "
#270
b1111111111110000000000000000000000000000000000000000000011111111 #
b1101 "
#290
b1111111100000000000000000000000000000000000000000000111111111111 #
b1110 "
#310
b1111000000000000000000000000000000000000000000001111111111111111 #
b1111 "