From 7376c920bc22332e071f9af6bc8104117c73a877 Mon Sep 17 00:00:00 2001 From: Raphael Jacquot Date: Fri, 22 Feb 2019 19:30:53 +0100 Subject: [PATCH] change the clock phase generation from a counter to a shift register adapt everywhere needed --- saturn_alu.v | 43 +++++++++++---------- saturn_bus_ctrl.v | 93 +++++++++++++++++++++++++------------------- saturn_core.v | 98 ++++++++++++++--------------------------------- saturn_test_rom.v | 17 ++++---- 4 files changed, 112 insertions(+), 139 deletions(-) diff --git a/saturn_alu.v b/saturn_alu.v index e7aeb5e..0d0e920 100644 --- a/saturn_alu.v +++ b/saturn_alu.v @@ -38,13 +38,8 @@ module saturn_alu ( i_clk, i_reset, - i_clk_ph, + i_phases, i_cycle_ctr, - i_en_alu_dump, - i_en_alu_prep, - i_en_alu_calc, - i_en_alu_init, - i_en_alu_save, i_stalled, o_bus_address, @@ -100,13 +95,8 @@ module saturn_alu ( input wire [0:0] i_clk; input wire [0:0] i_reset; -input wire [1:0] i_clk_ph; +input wire [3:0] i_phases; input wire [31:0] i_cycle_ctr; -input wire [0:0] i_en_alu_dump; -input wire [0:0] i_en_alu_prep; -input wire [0:0] i_en_alu_calc; -input wire [0:0] i_en_alu_init; -input wire [0:0] i_en_alu_save; input wire [0:0] i_stalled; /* @@ -178,18 +168,28 @@ assign o_pc = PC; * */ -wire [1:0] phase; -assign phase = i_clk_ph - 2'b01; - wire [0:0] phase_0; wire [0:0] phase_1; wire [0:0] phase_2; wire [0:0] phase_3; -assign phase_0 = (phase == 0); -assign phase_1 = (phase == 1); -assign phase_2 = (phase == 2); -assign phase_3 = (phase == 3); +assign phase_0 = i_phases[0]; +assign phase_1 = i_phases[1]; +assign phase_2 = i_phases[2]; +assign phase_3 = i_phases[3]; + +reg [1:0] phase; + +always @(*) begin + phase = 2'd0; + case (1'b1) + phase_0: phase = 2'd0; + phase_1: phase = 2'd1; + phase_2: phase = 2'd2; + phase_3: phase = 2'd3; + default: phase = 2'd0; + endcase +end wire alu_active; @@ -456,6 +456,7 @@ assign dest_ptr = dest_D0 || dest_D1; reg [0:0] just_reset; always @(posedge i_clk) begin + if (just_reset && !i_reset) $display("ALU_INIT %0d: [%d] CLEARING JUST_RESET", phase, i_cycle_ctr); @@ -1085,9 +1086,9 @@ end `ifdef SIM wire do_reg_dump; wire do_alu_shpc; -assign do_reg_dump = alu_active && i_en_alu_dump && !o_bus_load_pc && +assign do_reg_dump = alu_active && phase_0 && !o_bus_load_pc && i_ins_decoded && !o_alu_stall_dec; -assign do_alu_shpc = alu_active && i_en_alu_dump; +assign do_alu_shpc = alu_active && phase_0; `endif diff --git a/saturn_bus_ctrl.v b/saturn_bus_ctrl.v index c81d8d2..6bf5d4c 100644 --- a/saturn_bus_ctrl.v +++ b/saturn_bus_ctrl.v @@ -38,7 +38,7 @@ module saturn_bus_ctrl ( i_clk, i_reset, - i_phase, + i_phases, i_cycle_ctr, i_stalled, i_alu_busy, @@ -74,7 +74,7 @@ module saturn_bus_ctrl ( input wire [0:0] i_clk; input wire [0:0] i_reset; -input wire [1:0] i_phase; +input wire [3:0] i_phases; input wire [31:0] i_cycle_ctr; input wire [0:0] i_stalled; input wire [0:0] i_alu_busy; @@ -120,10 +120,10 @@ wire [0:0] bus_start; wire [0:0] bus_active; reg [0:0] strobe_on; assign bus_reset_event = !i_reset && !i_stalled && bus_out_of_reset; -assign reset_bus = bus_reset_event && (i_phase == 0) && !strobe_on; -assign bus_start = bus_reset_event && (i_phase == 1) && strobe_on; +assign reset_bus = bus_reset_event && phase_0 && !strobe_on; +assign bus_start = bus_reset_event && phase_1 && strobe_on; assign bus_active = !i_reset && !i_stalled && !bus_out_of_reset; -assign o_bus_strobe = (i_phase == 1) && strobe_on; +assign o_bus_strobe = phase_1 && strobe_on; // events phases @@ -132,10 +132,23 @@ wire [0:0] phase_1; wire [0:0] phase_2; wire [0:0] phase_3; -assign phase_0 = bus_active && (i_phase == 0); -assign phase_1 = bus_active && (i_phase == 1); -assign phase_2 = bus_active && (i_phase == 2); -assign phase_3 = bus_active && (i_phase == 3); +assign phase_0 = i_phases[0]; +assign phase_1 = i_phases[1]; +assign phase_2 = i_phases[2]; +assign phase_3 = i_phases[3]; + +reg [1:0] phase; + +always @(*) begin + phase = 2'd0; + case (1'b1) + phase_0: phase = 2'd0; + phase_1: phase = 2'd1; + phase_2: phase = 2'd2; + phase_3: phase = 2'd3; + default: phase = 2'd0; + endcase +end /****************************************************************************** * @@ -443,7 +456,7 @@ initial begin */ // $monitor({"BUS - clk %b | ph %0d | osta %b | iabs %b | ", // "LC_load_pc %b | addr_loop_done %b | do_auto_PC_READ_TST %b | cmd_LOAD_PC_F %b"}, - // i_clk, i_phase, o_stall_alu, i_alu_busy, + // i_clk, phase, o_stall_alu, i_alu_busy, // LC_load_pc, addr_loop_done, do_auto_PC_READ_TST, cmd_LOAD_PC_F); /* @@ -451,7 +464,7 @@ initial begin */ // $monitor({"BUS - clk %b | ph %0d | osta %b | iabs %b | ", // "cmd_LOAD_DP_F %b | addr_loop_done %b | do_auto_DP_READ_TST %b"}, - // i_clk, i_phase, o_stall_alu, i_alu_busy, + // i_clk, phase, o_stall_alu, i_alu_busy, // cmd_LOAD_DP_F, addr_loop_done, do_auto_DP_READ_TST); /* @@ -459,7 +472,7 @@ initial begin */ // $monitor({"BUS - clk %b | ph %0d | osta %b | iabs %b | ", // "i_cmd_dp_write %b | cmd_LOAD_DP_F %b | addr_loop_done %b | do_auto_DP_READ_TST %b | cmd_DP_WRITE_F0 %b | cnd_DP_WRITE_F1 %b"}, - // i_clk, i_phase, o_stall_alu, i_alu_busy, + // i_clk, phase, o_stall_alu, i_alu_busy, // i_cmd_dp_write, cmd_LOAD_DP_F, addr_loop_done, do_auto_DP_READ_TST, cmd_DP_WRITE_F0, cmd_DP_WRITE_F1); /* @@ -467,14 +480,14 @@ initial begin */ // $monitor({"BUS - clk %b | ph %0d | osta %b | iabs %b | ", // "i_cmd_dp_read %b | cmd_LOAD_DP_F %b | addr_loop_done %b | do_auto_DP_READ_TST %b | cmd_DP_WRITE_F0 %b | cnd_DP_WRITE_F1 %b"}, - // i_clk, i_phase, o_stall_alu, i_alu_busy, + // i_clk, phase, o_stall_alu, i_alu_busy, // i_cmd_dp_read, cmd_LOAD_DP_F, addr_loop_done, do_auto_DP_READ_TST, cmd_DP_WRITE_F0, cmd_DP_WRITE_F1); /* debug strobe for reading */ // $monitor({"BUS - clk %b | ph %0d | osta %b | iabs %b | ", // "cPR %b | cLP %b | dRP %b | dRD %b | dcs %b | dral %b | drs %b | stro %b | str %b"}, - // i_clk, i_phase, o_stall_alu, i_alu_busy, + // i_clk, phase, o_stall_alu, i_alu_busy, // cmd_PC_READ_STR, cmd_LOAD_PC_STR, // do_READ_PC_STR, do_read_dp_str, // do_cmd_strobe, do_run_addr_loop, do_read_strobe, @@ -486,7 +499,7 @@ initial begin // $monitor({"BUS - clk %b | ph %0d | osta %b | iabs %b | ", // "i_cmd_config %b | cmd_CONFIGURE_F0 %b | is_loop_finished %b | cmd_CONFIGURE_F1 %b | cmd_PC_READ_F %b"}, - // i_clk, i_phase, o_stall_alu, i_alu_busy, + // i_clk, phase, o_stall_alu, i_alu_busy, // i_cmd_config, cmd_CONFIGURE_F0, is_loop_finished, cmd_CONFIGURE_F1, cmd_PC_READ_F); /* @@ -494,7 +507,7 @@ initial begin */ // $monitor({"BUS - clk %b | ph %0d | osta %b | iabs %b | ", // "i_cmd_reset %b | cmd_RESET_F %b | cmd_PC_READ_F %b"}, - // i_clk, i_phase, o_stall_alu, i_alu_busy, + // i_clk, phase, o_stall_alu, i_alu_busy, // i_cmd_reset, cmd_RESET_F, cmd_PC_READ_F); `endif end @@ -547,7 +560,7 @@ always @(posedge i_clk) begin */ if (cmd_PC_READ_0) begin - $display("BUS_CTRL %1d: [%d] PC_READ", i_phase, i_cycle_ctr); + $display("BUS_CTRL %1d: [%d] PC_READ", phase, i_cycle_ctr); cmd_PC_READ_F <= 1; last_cmd <= `BUSCMD_PC_READ; o_bus_data <= `BUSCMD_PC_READ; @@ -560,7 +573,7 @@ always @(posedge i_clk) begin */ if (cmd_DP_WRITE_0) begin - $display("BUS_CTRL %1d: [%d] DP_WRITE (%0d nibble to write - ctr %0d)", i_phase, i_cycle_ctr, i_xfr_cnt + 1, o_data_ptr); + $display("BUS_CTRL %1d: [%d] DP_WRITE (%0d nibble to write - ctr %0d)", phase, i_cycle_ctr, i_xfr_cnt + 1, o_data_ptr); cmd_DP_WRITE_F0 <= 1; o_data_ptr <= 0; last_cmd <= `BUSCMD_DP_WRITE; @@ -570,22 +583,22 @@ always @(posedge i_clk) begin end if (cmd_DP_WRITE_1) begin - $display("BUS_CTRL %1d: [%d] cmd_DP_WRITE_1 (sets cmd_DP_WRITE_F1)", i_phase, i_cycle_ctr); + $display("BUS_CTRL %1d: [%d] cmd_DP_WRITE_1 (sets cmd_DP_WRITE_F1)", phase, i_cycle_ctr); cmd_DP_WRITE_F1 <= 1; // o_stall_alu <= 1; end if (cmd_DP_WRITE_US0) begin - $display("BUS_CTRL %1d: [%d] cmd_DP_WRITE_US0", i_phase, i_cycle_ctr); + $display("BUS_CTRL %1d: [%d] cmd_DP_WRITE_US0", phase, i_cycle_ctr); end if (cmd_DP_WRITE_US1) begin - $display("BUS_CTRL %1d: [%d] cmd_DP_WRITE_US1 (signal done)", i_phase, i_cycle_ctr); + $display("BUS_CTRL %1d: [%d] cmd_DP_WRITE_US1 (signal done)", phase, i_cycle_ctr); o_bus_done <= 1; end if (cmd_DP_WRITE_C) begin - $display("BUS_CTRL %1d: [%d] cmd_DP_WRITE_C", i_phase, i_cycle_ctr); + $display("BUS_CTRL %1d: [%d] cmd_DP_WRITE_C", phase, i_cycle_ctr); o_bus_done <= 0; end @@ -596,7 +609,7 @@ always @(posedge i_clk) begin */ if (cmd_LOAD_PC_0) begin - $display("BUS_CTRL %1d: [%d] LOAD_PC [%5h]", i_phase, i_cycle_ctr, i_address); + $display("BUS_CTRL %1d: [%d] LOAD_PC [%5h]", phase, i_cycle_ctr, i_address); cmd_LOAD_PC_F <= 1; last_cmd <= `BUSCMD_LOAD_PC; o_bus_data <= `BUSCMD_LOAD_PC; @@ -608,13 +621,13 @@ always @(posedge i_clk) begin /* automatic PC_READ after LOAD_PC */ if (do_auto_PC_READ_0) begin - $display("BUS_CTRL %1d: [%d] auto PC_READ", i_phase, i_cycle_ctr); + $display("BUS_CTRL %1d: [%d] auto PC_READ", phase, i_cycle_ctr); last_cmd <= `BUSCMD_PC_READ; end `ifdef DEBUG_CTRL if (do_auto_PC_READ_US0) begin - $display("BUS_CTRL %1d: [%d] auto PC_READ - unstall", i_phase, i_cycle_ctr); + $display("BUS_CTRL %1d: [%d] auto PC_READ - unstall", phase, i_cycle_ctr); end `endif @@ -625,7 +638,7 @@ always @(posedge i_clk) begin */ if (cmd_LOAD_DP_0) begin - $display("BUS_CTRL %1d: [%d] LOAD_DP [%5h]", i_phase, i_cycle_ctr, i_address); + $display("BUS_CTRL %1d: [%d] LOAD_DP [%5h]", phase, i_cycle_ctr, i_address); cmd_LOAD_DP_F <= 1; last_cmd <= `BUSCMD_LOAD_DP; o_bus_data <= `BUSCMD_LOAD_DP; @@ -637,7 +650,7 @@ always @(posedge i_clk) begin /* automatic DP_READ after LOAD_DP */ if (do_auto_DP_READ_0) begin - $display("BUS_CTRL %1d: [%d] auto DP_READ (%0d nibble to read - ctr %0d)", i_phase, i_cycle_ctr, i_xfr_cnt + 1, o_data_ptr); + $display("BUS_CTRL %1d: [%d] auto DP_READ (%0d nibble to read - ctr %0d)", phase, i_cycle_ctr, i_xfr_cnt + 1, o_data_ptr); cmd_DP_READ_F <= 1; last_cmd <= `BUSCMD_DP_READ; end @@ -649,7 +662,7 @@ always @(posedge i_clk) begin *****************************************************************************/ if (cmd_CONFIGURE_0) begin - $display("BUS_CTRL %1d: [%d] CONFIGURE [%5h]", i_phase, i_cycle_ctr, i_address); + $display("BUS_CTRL %1d: [%d] CONFIGURE [%5h]", phase, i_cycle_ctr, i_address); cmd_CONFIGURE_F0 <= 1; last_cmd <= `BUSCMD_CONFIGURE; o_bus_data <= `BUSCMD_CONFIGURE; @@ -659,7 +672,7 @@ always @(posedge i_clk) begin end if (cmd_CONFIGURE_1) begin - $display("BUS_CTRL %1d: [%d] set cmd_CONFIGURE_F1", i_phase, i_cycle_ctr); + $display("BUS_CTRL %1d: [%d] set cmd_CONFIGURE_F1", phase, i_cycle_ctr); cmd_CONFIGURE_F1 <= 1; end @@ -670,12 +683,12 @@ always @(posedge i_clk) begin *****************************************************************************/ if (cmd_RESET_ST0) begin - // $display("BUS_CTRL %1d: [%d] reset stall", i_phase, i_cycle_ctr); + // $display("BUS_CTRL %1d: [%d] reset stall", phase, i_cycle_ctr); o_stall_alu <= 1; end if (cmd_RESET_0) begin - $display("BUS_CTRL %1d: [%d] RESET", i_phase, i_cycle_ctr); + $display("BUS_CTRL %1d: [%d] RESET", phase, i_cycle_ctr); cmd_RESET_F <= 1; last_cmd <= `BUSCMD_RESET; o_bus_data <= `BUSCMD_RESET; @@ -690,7 +703,7 @@ always @(posedge i_clk) begin ***************************************************************************/ if (do_init_addr_loop) begin - // $display("BUS_CTRL %1d: [%d] init addr loop", i_phase, i_cycle_ctr); + // $display("BUS_CTRL %1d: [%d] init addr loop", phase, i_cycle_ctr); addr_loop_done <= 0; o_data_ptr <= 0; run_addr_loop <= 1; @@ -699,7 +712,7 @@ always @(posedge i_clk) begin if (do_run_addr_loop) begin $write("BUS_CTRL %1d: [%d] ADDR(%0d)-> %h ", - i_phase, i_cycle_ctr, o_data_ptr, + phase, i_cycle_ctr, o_data_ptr, LC_load_pc?i_address[o_data_ptr*4+:4]:i_data_nibl); if (will_loop_finish) $write("done"); $write("\n"); @@ -713,7 +726,7 @@ always @(posedge i_clk) begin end if (do_reset_loop_counter) begin - // $display("BUS_CTRL %1d: [%d] reset loop counter", i_phase, i_cycle_ctr); + // $display("BUS_CTRL %1d: [%d] reset loop counter", phase, i_cycle_ctr); o_data_ptr <= 0; end @@ -722,20 +735,20 @@ always @(posedge i_clk) begin if (do_unstall) begin `ifdef DEBUG_CTRL - $display("BUS_CTRL %1d: [%d] remove stall", i_phase, i_cycle_ctr); + $display("BUS_CTRL %1d: [%d] remove stall", phase, i_cycle_ctr); `endif o_stall_alu <= 0; end if (do_load_clean) begin - $display("BUS_CTRL %1d: [%d] cleanup after load", i_phase, i_cycle_ctr); + $display("BUS_CTRL %1d: [%d] cleanup after load", phase, i_cycle_ctr); cmd_LOAD_PC_F <= 0; cmd_LOAD_DP_F <= 0; o_data_ptr <= 0; end if (do_clean) begin - $display("BUS_CTRL %1d: [%d] cleanup", i_phase, i_cycle_ctr); + $display("BUS_CTRL %1d: [%d] cleanup", phase, i_cycle_ctr); cmd_PC_READ_F <= 0; cmd_DP_READ_F <= 0; cmd_DP_WRITE_F0 <= 0; @@ -763,17 +776,17 @@ always @(posedge i_clk) begin if (do_read) begin o_nibble <= i_bus_data; - $display("BUS_CTRL %1d: [%d] READ %h", i_phase, i_cycle_ctr, i_bus_data); + $display("BUS_CTRL %1d: [%d] READ %h", phase, i_cycle_ctr, i_bus_data); end if (do_WRITE_DP_0) begin - $display("BUS_CTRL %1d: [%d] WRITE %h %0d/%0d (%0d to go)", i_phase, i_cycle_ctr, i_data_nibl, o_data_ptr, i_xfr_cnt, i_xfr_cnt - o_data_ptr); + $display("BUS_CTRL %1d: [%d] WRITE %h %0d/%0d (%0d to go)", phase, i_cycle_ctr, i_data_nibl, o_data_ptr, i_xfr_cnt, i_xfr_cnt - o_data_ptr); o_bus_data <= i_data_nibl; o_data_ptr <= o_data_ptr + 1; end if (do_read_stalled_by_alu) begin - $display("BUS_CTRL %1d: [%d] read stall (alu)", i_phase, i_cycle_ctr); + $display("BUS_CTRL %1d: [%d] read stall (alu)", phase, i_cycle_ctr); end if (do_remove_strobe) begin diff --git a/saturn_core.v b/saturn_core.v index 80758ca..fc4b710 100644 --- a/saturn_core.v +++ b/saturn_core.v @@ -130,8 +130,8 @@ saturn_decoder m_decoder ( .i_clk (i_clk), .i_reset (i_reset), .i_cycles (cycle_ctr), - .i_en_dbg (ck_debugger), - .i_en_dec (ck_inst_dec), + .i_en_dbg (phase_0), + .i_en_dec (phase_2), .i_pc (reg_pc), .i_bus_load_pc (alu_bus_load_pc), .i_stalled (dec_stalled), @@ -215,13 +215,8 @@ wire [0:0] ins_unconfig; saturn_alu m_alu ( .i_clk (i_clk), .i_reset (i_reset), - .i_clk_ph (clk_phase[1:0]), + .i_phases (clk_phases), .i_cycle_ctr (cycle_ctr), - .i_en_alu_dump (ck_alu_dump), - .i_en_alu_prep (ck_alu_prep), - .i_en_alu_calc (ck_alu_calc), - .i_en_alu_init (ck_alu_init), - .i_en_alu_save (ck_alu_save), .i_stalled (alu_stalled), .o_bus_address (alu_bus_address), @@ -303,7 +298,7 @@ saturn_bus_ctrl m_bus_ctrl ( // basic stuff .i_clk (i_clk), .i_reset (i_reset), - .i_phase (o_phase), + .i_phases (clk_phases), .i_cycle_ctr (cycle_ctr), .i_stalled (mem_ctrl_stall), .i_alu_busy (dec_stalled), @@ -346,25 +341,10 @@ wire [3:0] ctrl_bus_nibble_in; // `define DEBUG_CLOCKS initial begin - clk_phase = 0; + clk_phases = 0; - ck_debugger = 0; // phase 0 - - ck_bus_send = 0; // phase 0 - ck_bus_recv = 0; // phase 1 - ck_bus_ecmd = 0; // phase 3 - - ck_inst_dec = 0; // phase 2 - ck_inst_exe = 0; // phase 3 - - ck_alu_dump = 0; - ck_alu_prep = 0; // phase 1 - ck_alu_calc = 0; // phase 2 - ck_alu_init = 0; // phase 0 - ck_alu_save = 0; // phase 3 - - clock_end = 0; - cycle_ctr = 0; + clock_end = 0; + cycle_ctr = 0; mem_ctrl_stall = 0; @@ -384,57 +364,39 @@ initial begin // //-------------------------------------------------------------------------------------------------- +reg [3:0] clk_phases; + +wire phase_0; +wire phase_1; +wire phase_2; +wire phase_3; + +assign phase_0 = clk_phases[0]; +assign phase_1 = clk_phases[1]; +assign phase_2 = clk_phases[2]; +assign phase_3 = clk_phases[3]; + always @(posedge i_clk) begin - if (!i_reset) begin - clk_phase <= clk_phase + 1; - ck_debugger <= clk_phase[1:0] == `PH_DEBUGGER; - ck_bus_send <= clk_phase[1:0] == `PH_BUS_SEND; - ck_bus_recv <= clk_phase[1:0] == `PH_BUS_RECV; - ck_bus_ecmd <= clk_phase[1:0] == `PH_BUS_ECMD; + clk_phases <= {clk_phases[2:0], clk_phases[3]}; - ck_inst_dec <= clk_phase[1:0] == `PH_INST_DEC; - ck_inst_exe <= clk_phase[1:0] == `PH_INST_EXE; + cycle_ctr <= cycle_ctr + { {31{1'b0}}, phase_0 }; + if (cycle_ctr == (max_cycle + 1)) begin + $display(".-----------------------------."); + $display("| OUT OF CYCLES %d |", cycle_ctr); + $display("`-----------------------------´"); + clock_end <= 1; + end - ck_alu_dump <= clk_phase[1:0] == `PH_ALU_DUMP; - ck_alu_init <= clk_phase[1:0] == `PH_ALU_INIT; - ck_alu_prep <= clk_phase[1:0] == `PH_ALU_PREP; - ck_alu_calc <= clk_phase[1:0] == `PH_ALU_CALC; - ck_alu_save <= clk_phase[1:0] == `PH_ALU_SAVE; + if (i_reset) begin - cycle_ctr <= cycle_ctr + { {31{1'b0}}, (clk_phase[1:0] == `PH_BUS_SEND) }; - if (cycle_ctr == (max_cycle + 1)) begin - $display(".-----------------------------."); - $display("| OUT OF CYCLES %d |", cycle_ctr); - $display("`-----------------------------´"); - clock_end <= 1; - end - end else begin - clk_phase <= ~0; - - ck_debugger <= 0; - - ck_bus_send <= 0; - ck_bus_recv <= 0; - ck_bus_ecmd <= 0; - - ck_inst_dec <= 0; - ck_inst_exe <= 0; - - ck_alu_dump <= 0; - ck_alu_init <= 0; - ck_alu_prep <= 0; - ck_alu_calc <= 0; - ck_alu_save <= 0; + clk_phases <= 4'b0001; clock_end <= 0; cycle_ctr <= ~0; max_cycle <= 100; mem_ctrl_stall <= 0; -`ifndef SIM - led[7:0] <= reg_pc[7:0]; -`endif end end @@ -485,8 +447,6 @@ saturn_core saturn ( ); saturn_test_rom rom ( - .i_phase (core_phase), - .i_reset (core_bus_reset), .i_bus_data_in (core_bus_data_out), .o_bus_data_out (core_bus_data_in), diff --git a/saturn_test_rom.v b/saturn_test_rom.v index a8fceb9..52f86b3 100644 --- a/saturn_test_rom.v +++ b/saturn_test_rom.v @@ -30,7 +30,6 @@ ****************************************************************************/ module saturn_test_rom ( - i_phase, i_reset, i_bus_data_in, o_bus_data_out, @@ -73,8 +72,8 @@ assign s_dp_read = (last_bus_cmd == `BUSCMD_DP_READ); assign s_dp_write = (last_bus_cmd == `BUSCMD_DP_WRITE); initial begin - // $readmemh("rom-gx-r.hex", rom, 0, 2**`ROMBITS-1); - $readmemh("testrom-2.hex", rom, 0, 2**`ROMBITS-1); + $readmemh("rom-gx-r.hex", rom, 0, 2**`ROMBITS-1); + // $readmemh("testrom-2.hex", rom, 0, 2**`ROMBITS-1); // $monitor("rst %b | strb %b | c/d %b | bus_i %h | bus_o %h | last %h | slpc %b | addr_c %0d | lpc %5h | ldp %5h", // i_reset, i_bus_strobe, i_bus_cmd_data, i_bus_data_in, o_bus_data_out, // last_bus_cmd, s_load_pc, addr_c, local_pc, local_dp); @@ -96,7 +95,7 @@ always @(posedge i_bus_strobe) begin if (!i_bus_cmd_data) begin - $write("ROM %0d: [%d] COMMAND ", i_phase, cycles); + $write("ROM : [%d] COMMAND ", cycles); case (i_bus_data_in) `BUSCMD_PC_READ: $write("PC_READ"); // 2 `BUSCMD_DP_WRITE: $write("DP_WRITE"); // 5 @@ -111,7 +110,7 @@ always @(posedge i_bus_strobe) begin end if (i_bus_cmd_data && s_load_pc) begin - $display("ROM %0d: [%d] ADDR_IN(%0d) %h => PC [%5h]", i_phase, cycles, addr_c, i_bus_data_in, local_pc); + $display("ROM : [%d] ADDR_IN(%0d) %h => PC [%5h]", cycles, addr_c, i_bus_data_in, local_pc); local_pc[addr_c*4+:4] <= i_bus_data_in; if (addr_c == 4) $display("ROM : [%d] auto PC_READ [%5h]", cycles, {i_bus_data_in, local_pc[15:0]}); last_bus_cmd <= (addr_c == 4)?`BUSCMD_PC_READ:last_bus_cmd; @@ -119,7 +118,7 @@ always @(posedge i_bus_strobe) begin end if (i_bus_cmd_data && s_load_dp) begin - $display("ROM %0d: [%d] ADDR_IN(%0d) %h => DP [%5h]", i_phase, cycles, addr_c, i_bus_data_in, local_dp); + $display("ROM : [%d] ADDR_IN(%0d) %h => DP [%5h]", cycles, addr_c, i_bus_data_in, local_dp); local_dp[addr_c*4+:4] <= i_bus_data_in; if (addr_c == 4) $display("ROM : [%d] auto DP_READ [%5h]", cycles, {i_bus_data_in, local_dp[15:0]}); last_bus_cmd <= (addr_c == 4)?`BUSCMD_DP_READ:last_bus_cmd; @@ -128,18 +127,18 @@ always @(posedge i_bus_strobe) begin if (i_bus_cmd_data && s_pc_read) begin o_bus_data_out <= rom[local_pc[`ROMBITS-1:0]]; - $display("ROM %0d: [%d] %h <= PC_READ [%5h]", i_phase, cycles, rom[local_pc[`ROMBITS-1:0]], local_pc); + $display("ROM : [%d] %h <= PC_READ [%5h]", cycles, rom[local_pc[`ROMBITS-1:0]], local_pc); local_pc <= local_pc + 1; end if (i_bus_cmd_data && s_dp_read) begin o_bus_data_out <= rom[local_dp[`ROMBITS-1:0]]; - $display("ROM %0d: [%d] %h <= DP_READ [%5h]", i_phase, cycles, rom[local_dp[`ROMBITS-1:0]], local_dp); + $display("ROM : [%d] %h <= DP_READ [%5h]", cycles, rom[local_dp[`ROMBITS-1:0]], local_dp); local_dp <= local_dp + 1; end if (i_bus_cmd_data && s_dp_write) begin - $display("ROM %0d: [%d] %h => DP_WRITE [%5h] (ignored)", i_phase, cycles, i_bus_data_in, local_dp); + $display("ROM : [%d] %h => DP_WRITE [%5h] (ignored)", cycles, i_bus_data_in, local_dp); local_dp <= local_dp + 1; end