fix some verilator warnings

.gitignore

@@ -1,3 +1,8 @@
 saturn_core.json
 rom_tb
-saturn_core.json
+obj_dir/Vsaturn_core.cpp
+obj_dir/Vsaturn_core.h
+obj_dir/Vsaturn_core.mk
+obj_dir/Vsaturn_core__Syms.cpp
+obj_dir/Vsaturn_core__Syms.h
+obj_dir/Vsaturn_core_classes.mk

compile

@@ -2,4 +2,4 @@
 #yosys -p "synth_ecp5 -top mask_gen -json mask_gen.json" mask_gen.v
 #nextpnr-ecp5 --gui --um-85k --speed 6 --freq 5 --json mask_gen.json --save mask_gen.ecp5 
 yosys -p "synth_ecp5 -top saturn_core -json saturn_core.json" saturn_core.v
-nextpnr-ecp5 --gui --um-85k --speed 6 --freq 5 --lpf ulx3s_v20.lpf --json saturn_core.json --save saturn_core.ecp5 
+nextpnr-ecp5 --gui --um-85k --speed 6 --freq 5 --lpf ulx3s_v20.lpf --textcfg empty_lfe5u-85f.config --json saturn_core.json --save saturn_core.ecp5 

empty_lfe5u-85f.config

@@ -0,0 +1,534 @@
+.device LFE5U-85F
+
+.tile CIB_R10C3:PVT_COUNT2
+unknown: F2B0
+unknown: F3B0
+unknown: F5B0
+unknown: F11B0
+unknown: F13B0
+
+
+.tile CIB_R5C125:CIB_PLL1
+enum: CIB.JA3MUX 0
+enum: CIB.JB3MUX 0
+
+
+.tile CIB_R5C1:CIB_PLL1
+enum: CIB.JA3MUX 0
+enum: CIB.JB3MUX 0
+
+
+.tile CIB_R94C123:CIB_PLL3
+enum: CIB.JA3MUX 0
+enum: CIB.JB3MUX 0
+
+
+.tile CIB_R94C3:CIB_PLL3
+enum: CIB.JA3MUX 0
+enum: CIB.JB3MUX 0
+
+
+.tile CIB_R94C46:VCIB_DCU0
+enum: CIB.JA1MUX 0
+enum: CIB.JA3MUX 0
+enum: CIB.JA5MUX 0
+enum: CIB.JA7MUX 0
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JC0MUX 0
+enum: CIB.JC2MUX 0
+enum: CIB.JC4MUX 0
+enum: CIB.JC6MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R94C47:VCIB_DCUA
+enum: CIB.JA1MUX 0
+enum: CIB.JA3MUX 0
+enum: CIB.JA5MUX 0
+enum: CIB.JA7MUX 0
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JC0MUX 0
+enum: CIB.JC2MUX 0
+enum: CIB.JC4MUX 0
+enum: CIB.JC6MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R94C48:VCIB_DCUB
+enum: CIB.JA1MUX 0
+enum: CIB.JA3MUX 0
+enum: CIB.JA5MUX 0
+enum: CIB.JA7MUX 0
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JC0MUX 0
+enum: CIB.JC2MUX 0
+enum: CIB.JC4MUX 0
+enum: CIB.JC6MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R94C49:VCIB_DCUC
+enum: CIB.JA1MUX 0
+enum: CIB.JA3MUX 0
+enum: CIB.JA5MUX 0
+enum: CIB.JA7MUX 0
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JC0MUX 0
+enum: CIB.JC2MUX 0
+enum: CIB.JC4MUX 0
+enum: CIB.JC6MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R94C50:VCIB_DCUD
+enum: CIB.JA1MUX 0
+enum: CIB.JA5MUX 0
+enum: CIB.JA7MUX 0
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JC0MUX 0
+enum: CIB.JC2MUX 0
+enum: CIB.JC4MUX 0
+enum: CIB.JC6MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R94C51:VCIB_DCUF
+enum: CIB.JA1MUX 0
+enum: CIB.JA3MUX 0
+enum: CIB.JA5MUX 0
+enum: CIB.JA7MUX 0
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JC0MUX 0
+enum: CIB.JC2MUX 0
+enum: CIB.JC4MUX 0
+enum: CIB.JC6MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R94C52:VCIB_DCU3
+enum: CIB.JA5MUX 0
+enum: CIB.JA7MUX 0
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JC0MUX 0
+enum: CIB.JC4MUX 0
+enum: CIB.JC6MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R94C53:VCIB_DCU2
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R94C54:VCIB_DCUG
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R94C55:VCIB_DCUH
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R94C56:VCIB_DCUI
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R94C57:VCIB_DCU1
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+
+
+.tile CIB_R94C6:CIB_EFB0
+enum: CIB.JB3MUX 0
+enum: CIB.JC6MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R94C71:VCIB_DCU0
+enum: CIB.JA1MUX 0
+enum: CIB.JA3MUX 0
+enum: CIB.JA5MUX 0
+enum: CIB.JA7MUX 0
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JC0MUX 0
+enum: CIB.JC2MUX 0
+enum: CIB.JC4MUX 0
+enum: CIB.JC6MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R94C72:VCIB_DCUA
+enum: CIB.JA1MUX 0
+enum: CIB.JA3MUX 0
+enum: CIB.JA5MUX 0
+enum: CIB.JA7MUX 0
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JC0MUX 0
+enum: CIB.JC2MUX 0
+enum: CIB.JC4MUX 0
+enum: CIB.JC6MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R94C73:VCIB_DCUB
+enum: CIB.JA1MUX 0
+enum: CIB.JA3MUX 0
+enum: CIB.JA5MUX 0
+enum: CIB.JA7MUX 0
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JC0MUX 0
+enum: CIB.JC2MUX 0
+enum: CIB.JC4MUX 0
+enum: CIB.JC6MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R94C74:VCIB_DCUC
+enum: CIB.JA1MUX 0
+enum: CIB.JA3MUX 0
+enum: CIB.JA5MUX 0
+enum: CIB.JA7MUX 0
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JC0MUX 0
+enum: CIB.JC2MUX 0
+enum: CIB.JC4MUX 0
+enum: CIB.JC6MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R94C75:VCIB_DCUD
+enum: CIB.JA1MUX 0
+enum: CIB.JA5MUX 0
+enum: CIB.JA7MUX 0
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JC0MUX 0
+enum: CIB.JC2MUX 0
+enum: CIB.JC4MUX 0
+enum: CIB.JC6MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R94C76:VCIB_DCUF
+enum: CIB.JA1MUX 0
+enum: CIB.JA3MUX 0
+enum: CIB.JA5MUX 0
+enum: CIB.JA7MUX 0
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JC0MUX 0
+enum: CIB.JC2MUX 0
+enum: CIB.JC4MUX 0
+enum: CIB.JC6MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R94C77:VCIB_DCU3
+enum: CIB.JA5MUX 0
+enum: CIB.JA7MUX 0
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JC0MUX 0
+enum: CIB.JC4MUX 0
+enum: CIB.JC6MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R94C78:VCIB_DCU2
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R94C79:VCIB_DCUG
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R94C7:CIB_EFB1
+enum: CIB.JA3MUX 0
+enum: CIB.JA4MUX 0
+enum: CIB.JA5MUX 0
+enum: CIB.JA6MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB4MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB6MUX 0
+enum: CIB.JC3MUX 0
+enum: CIB.JC4MUX 0
+enum: CIB.JC5MUX 0
+enum: CIB.JD3MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD5MUX 0
+
+
+.tile CIB_R94C80:VCIB_DCUH
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R94C81:VCIB_DCUI
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R94C82:VCIB_DCU1
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+
+
+.tile MIB_R22C67:CMUX_UL_0
+arc: G_DCS0CLK0 G_VPFN0000
+
+
+.tile MIB_R22C68:CMUX_UR_0
+arc: G_DCS0CLK1 G_VPFN0000
+
+
+.tile MIB_R70C67:CMUX_LL_0
+arc: G_DCS1CLK0 G_VPFN0000
+
+
+.tile MIB_R70C68:CMUX_LR_0
+arc: G_DCS1CLK1 G_VPFN0000
+
+
+.tile MIB_R95C101:PICB0
+unknown: F0B1
+
+
+.tile MIB_R95C102:PICB1
+unknown: F0B1
+
+
+.tile MIB_R95C103:PICB0
+unknown: F0B1
+
+
+.tile MIB_R95C104:PICB1
+unknown: F0B1
+
+
+.tile MIB_R95C105:PICB0
+unknown: F0B1
+
+
+.tile MIB_R95C106:PICB1
+unknown: F0B1
+
+
+.tile MIB_R95C107:PICB0
+unknown: F0B1
+
+
+.tile MIB_R95C108:PICB1
+unknown: F0B1
+
+
+.tile MIB_R95C110:PICB0
+unknown: F0B1
+
+
+.tile MIB_R95C111:PICB1
+unknown: F0B1
+
+
+.tile MIB_R95C112:PICB0
+unknown: F0B1
+
+
+.tile MIB_R95C113:PICB1
+unknown: F0B1
+
+
+.tile MIB_R95C114:PICB0
+unknown: F0B1
+
+
+.tile MIB_R95C115:PICB1
+unknown: F0B1
+
+
+.tile MIB_R95C116:PICB0
+unknown: F0B1
+
+
+.tile MIB_R95C117:PICB1
+unknown: F0B1
+
+
+.tile MIB_R95C119:PICB0
+unknown: F0B1
+
+
+.tile MIB_R95C120:PICB1
+unknown: F0B1
+
+
+.tile MIB_R95C121:PICB0
+unknown: F0B1
+
+
+.tile MIB_R95C122:PICB1
+unknown: F0B1
+
+
+.tile MIB_R95C4:EFB0_PICB0
+unknown: F54B1
+unknown: F56B1
+unknown: F82B1
+unknown: F94B1
+
+
+.tile MIB_R95C96:PICB0
+unknown: F0B1
+
+
+.tile MIB_R95C97:PICB1
+unknown: F0B1
+
+
+.tile MIB_R95C98:PICB0
+unknown: F0B1
+
+
+.tile MIB_R95C99:PICB1
+unknown: F0B1
+
+

run

@@ -1,4 +1,11 @@
 #!/bin/bash
+verilator -Wall -cc saturn_core.v
+VERILATOR_STATUS=$?
+if [ "VERILATOR_STATUS" != "0" ]
+then
+    echo "verilator fail"
+    exit
+fi
 #iverilog -v -Wall -DSIM -o mask_gen_tb mask_gen.v
 iverilog -v -Wall -DSIM -o rom_tb saturn_core.v
 IVERILOG_STATUS=$?

saturn_core.json

@@ -14309,22 +14309,68 @@
     "saturn_core": {
       "attributes": {
         "top": 1,
-        "src": "saturn_core.v:40"
+        "src": "saturn_core.v:49"
       },
       "ports": {
         "clk_25mhz": {
           "direction": "input",
           "bits": [ 2 ]
+        },
+        "btn": {
+          "direction": "input",
+          "bits": [ 3, 4, 5, 6, 7, 8, 9 ]
+        },
+        "wifi_gpio0": {
+          "direction": "output",
+          "bits": [ "1" ]
         }
       },
       "cells": {
       },
       "netnames": {
+        "btn": {
+          "hide_name": 0,
+          "bits": [ 3, 4, 5, 6, 7, 8, 9 ],
+          "attributes": {
+            "src": "saturn_core.v:51"
+          }
+        },
+        "calc_rom.clk": {
+          "hide_name": 0,
+          "bits": [ 2 ],
+          "attributes": {
+            "src": "saturn_core.v:157|saturn_core.v:12",
+            "unused_bits": "0"
+          }
+        },
+        "clk": {
+          "hide_name": 0,
+          "bits": [ 2 ],
+          "attributes": {
+            "src": "saturn_core.v:54",
+            "unused_bits": "0"
+          }
+        },
         "clk_25mhz": {
           "hide_name": 0,
           "bits": [ 2 ],
           "attributes": {
-            "src": "saturn_core.v:48"
+            "src": "saturn_core.v:50"
+          }
+        },
+        "reset": {
+          "hide_name": 0,
+          "bits": [ 4 ],
+          "attributes": {
+            "src": "saturn_core.v:55",
+            "unused_bits": "0"
+          }
+        },
+        "wifi_gpio0": {
+          "hide_name": 0,
+          "bits": [ "1" ],
+          "attributes": {
+            "src": "saturn_core.v:52"
           }
         }
       }

saturn_core.v

@@ -1,3 +1,5 @@
+`default_nettype none //
+
 /**************************************************************************************************
  *
  *
@@ -20,8 +22,7 @@ reg [3:0]	rom	[0:(2**20)-1];
 
 initial
 begin
-	if ( ROM_FILENAME != "" )
+	$readmemh( ROM_FILENAME, rom);
-		$readmemh( ROM_FILENAME, rom);
 end
 
 always @(posedge clk)
@@ -116,7 +117,7 @@ reg	[3:0]	runstate;
 reg	[31:0]	decstate;
 
 // memory access
-reg			rom_clock;
+//reg			rom_clock;
 reg	[19:0]	rom_address;
 reg			rom_enable;
 wire[3:0]	rom_nibble;
@@ -175,6 +176,7 @@ begin
 			rstk_ptr	<= 7;
 
 			PC			<= 0;
+			saved_PC	<= 0;
 			P			<= 0;
 			ST			<= 0;
 			HST			<= 0;
@@ -251,7 +253,7 @@ begin
 	if (runstate == READ_ROM_CLK)
 		begin				
 			//$display("READ_ROM_CLK");
-			rom_clock <= 1'b1;
+//			rom_clock <= 1'b1;
 			runstate <= READ_ROM_STR;
 		end
 
@@ -263,7 +265,7 @@ begin
 			//$display("PC: %h | read => %h", PC, rom_nibble);
 			PC <= PC + 1;
 			rom_enable <= 1'b0;
-			rom_clock <= 1'b0;
+//			rom_clock <= 1'b0;
 			runstate <= READ_ROM_VAL;
 		end
 
@@ -771,7 +773,7 @@ endtask
 			READ_ROM_VAL:
 				begin
 				  //$display("decstate %h | nibble %h", decstate, nibble);
-				  jump_base[load_ctr*4+:4] = nibble;
+				  jump_base[load_ctr*4+:4] <= nibble;
 `ifdef SIM
 				  $write("%1h", nibble);
 `endif
@@ -867,6 +869,11 @@ task decode_a_fs;
 endtask
 */
 end
+
+ / Verilator lint_off UNUSED
+ wire [N-1:0] unused;
+ assign unused = { }; 
+ / Verilator lint_on UNUSED
 endmodule
 
 `ifdef SIM