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debug the seial port

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This commit is contained in:
Raphael Jacquot 2019-03-04 17:01:59 +01:00
parent dc927031e4
commit 6f3f3ce73c
5 changed files with 50 additions and 20 deletions
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6
saturn_bus.v
View file

@ -28,7 +28,9 @@ module saturn_bus (
o_phase,
o_cycle_ctr,
o_char_to_send,
o_char_counter,
o_char_valid,
o_char_send,
i_serial_busy
);
@ -39,7 +41,9 @@ output wire [0:0] o_halt;
output wire [1:0] o_phase;
output wire [31:0] o_cycle_ctr;
output wire [7:0] o_char_to_send;
output wire [9:0] o_char_counter;
output wire [0:0] o_char_valid;
output wire [0:0] o_char_send;
input wire [0:0] i_serial_busy;
assign o_phase = phase;
@ -91,7 +95,9 @@ saturn_bus_controller bus_controller (
.o_debug_cycle (dbg_debug_cycle),
.o_char_to_send (o_char_to_send),
.o_char_counter (o_char_counter),
.o_char_valid (o_char_valid),
.o_char_send (o_char_send),
.i_serial_busy (i_serial_busy),
.o_halt (ctrl_halt)
);

6
saturn_bus_controller.v
View file

@ -35,7 +35,9 @@ module saturn_bus_controller (
o_debug_cycle,
o_char_to_send,
o_char_counter,
o_char_valid,
o_char_send,
i_serial_busy,
o_halt
);
@ -54,7 +56,9 @@ input wire [3:0] i_bus_nibble_in;
output wire [0:0] o_debug_cycle;
output wire [7:0] o_char_to_send;
output wire [9:0] o_char_counter;
output wire [0:0] o_char_valid;
output wire [0:0] o_char_send;
input wire [0:0] i_serial_busy;
output wire [0:0] o_halt;
@ -170,7 +174,9 @@ saturn_debugger debugger (
.i_instr_decoded (dec_instr_decoded),
.o_char_to_send (o_char_to_send),
.o_char_counter (o_char_counter),
.o_char_valid (o_char_valid),
.o_char_send (o_char_send),
.i_serial_busy (i_serial_busy)
);

16
saturn_debugger.v
View file

@ -58,7 +58,9 @@ module saturn_debugger (
/* output to leds */
o_char_to_send,
o_char_counter,
o_char_valid,
o_char_send,
i_serial_busy
);
@ -96,7 +98,10 @@ input wire [3:0] i_instr_type;
input wire [0:0] i_instr_decoded;
output reg [7:0] o_char_to_send;
output wire [9:0] o_char_counter;
assign o_char_counter = {1'b0, counter};
output reg [0:0] o_char_valid;
output reg [0:0] o_char_send;
input wire [0:0] i_serial_busy;
/**************************************************************************************************
@ -148,6 +153,7 @@ initial begin
o_dbg_register = `ALU_REG_NONE;
registers_done = 1'b0;
o_char_valid = 1'b0;
o_char_send = 1'b0;
carry = 1'b1;
end
@ -493,6 +499,10 @@ always @(posedge i_clk) begin
registers_ctr <= registers_ctr + 9'd1;
end
/*
*
*/
if (i_clk_en && o_debug_cycle && debug_done && !write_out) begin
$display("DEBUGGER %0d: [%d] end debugger cycle", i_phase, i_cycle_ctr);
counter <= 9'd0;
@ -500,7 +510,8 @@ always @(posedge i_clk) begin
end
/* writes the chars to the serial port */
if ( write_out && !o_char_valid && !i_serial_busy) begin
if (i_clk_en && write_out && !o_char_valid && !i_serial_busy) begin
o_char_send <= ~o_char_send;
o_char_to_send <= registers_str[counter];
o_char_valid <= 1'b1;
counter <= counter + 9'd1;
@ -516,8 +527,9 @@ always @(posedge i_clk) begin
o_debug_cycle <= 1'b0;
end
end
/* clear the char clock enable */
if (write_out && o_char_valid) begin
if (write_out && o_char_valid && i_serial_busy) begin
o_char_valid <= 1'b0;
end

14
saturn_serial.v
View file

@ -44,7 +44,7 @@ output wire [0:0] o_serial_busy;
*
*/
reg [9:0] clocking_reg;
reg [10:0] clocking_reg;
reg [9:0] data_reg;
`ifdef SIM
@ -65,7 +65,7 @@ reg [12:0] bit_delay;
initial begin
bit_delay = `BIT_DELAY_START;
clocking_reg = {10{1'b1}};
clocking_reg = {11{1'b1}};
data_reg = {10{1'b1}};
end
@ -74,16 +74,18 @@ assign o_serial_tx = data_reg[0];
always @(posedge i_clk) begin
bit_delay <= bit_delay + 13'd1;
// $display("%0d", bit_delay);
if (i_char_valid && !o_serial_busy) begin
// $display("serial storing char %c", i_char_to_send);
clocking_reg <= 10'b0;
clocking_reg <= 11'b0;
data_reg <= { 1'b1, i_char_to_send, 1'b0 };
bit_delay <= `BIT_DELAY_START;
end
if (!i_char_valid && o_serial_busy && bit_delay[`BIT_DELAY_TEST]) begin
// $display("%b %b", o_serial_tx, data_reg);
clocking_reg <= { 1'b1, clocking_reg[9:1] };
if (o_serial_busy && bit_delay[`BIT_DELAY_TEST]) begin
// $display("%b %b %b", o_serial_tx, data_reg, clocking_reg);
clocking_reg <= { 1'b1, clocking_reg[10:1] };
data_reg <= { 1'b1, data_reg[9:1] };
bit_delay <= `BIT_DELAY_START;
end

26
saturn_top.v
View file

@ -118,7 +118,9 @@ saturn_bus main_bus (
.o_phase (phase),
.o_cycle_ctr (cycle_ctr),
.o_char_to_send (char_to_send),
.o_char_counter (char_counter),
.o_char_valid (char_valid),
.o_char_send (char_send),
.i_serial_busy (serial_busy)
);
@ -138,13 +140,15 @@ wire [0:0] halt;
wire [1:0] phase;
wire [31:0] cycle_ctr;
wire [7:0] char_to_send;
wire [9:0] char_counter;
wire [0:0] char_valid;
wire [0:0] char_send;
wire [0:0] serial_busy;
/* 1/4 s */
// `define DELAY_START 26'h20A1F0
// `define TEST_BIT 23
`define DELAY_START 26'h20A1F0
`define TEST_BIT 23
/* 1/8 s */
// `define DELAY_START 26'h1050F8
@ -155,8 +159,8 @@ wire [0:0] serial_busy;
// `define TEST_BIT 21
/* 1/32 s */
`define DELAY_START 26'h4143E
`define TEST_BIT 20
// `define DELAY_START 26'h4143E
// `define TEST_BIT 20
initial begin
led = 8'h01;
@ -167,24 +171,24 @@ end
always @(posedge clk_25mhz) begin
delay <= delay + 26'b1;
led <= char_counter[7:0];
if (delay[`TEST_BIT]) begin
delay <= `DELAY_START;
reset <= btn[1];
clk2 <= ~clk2;
end
if (!clk2) begin
// led <= { halt, cycle_ctr[4:0], phase};
led <= { halt, cycle_ctr[6:0] };
end
led[7] <= clk2;
led[6] <= char_send;
if (clk2 && !halt) begin
clk_en <= 1'b1;
led <= char_to_send;
led[5] <= ~led[5];
end
if (clk_en)
if (clk_en) begin
clk_en <= 1'b0;
led[4] <= ~led[4];
end
end
endmodule