mirror of
https://github.com/sxpert/hp-saturn
synced 2025-01-20 10:26:31 +01:00
move the test rom to a separate module
This commit is contained in:
Raphael Jacquot
parent
4cce55e4ba
commit
6bb654944f
1 changed files with 167 additions and 20 deletions
185
saturn_core.v
185
saturn_core.v
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@ -26,31 +26,32 @@ module saturn_core (
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i_reset,
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o_halt,
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o_bus_reset,
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i_bus_data_in,
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o_bus_data_out,
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o_bus_strobe,
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o_bus_cmd_data
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o_bus_cmd_data,
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o_phase
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);
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input wire [0:0] i_clk;
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input wire [0:0] i_reset;
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output wire [0:0] o_halt;
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input wire [3:0] i_bus_data_in;
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output wire [3:0] o_bus_data_out;
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output wire [0:0] o_bus_strobe;
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output wire [0:0] o_bus_cmd_data;
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`else
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module saturn_core (
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clk_25mhz,
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btn,
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led,
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o_bus_reset,
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i_bus_data_in,
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o_bus_data_out,
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o_bus_strobe,
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o_bus_cmd_data
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o_bus_cmd_data,
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o_phase
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);
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input wire [0:0] clk_25mhz;
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@ -63,12 +64,18 @@ wire [0:0] i_reset;
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assign i_clk = clk_25mhz;
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assign i_reset = btn[1];
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`endif
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output wire [1:0] o_phase;
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assign o_phase = clk_phase + 3;
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output wire [0:0] o_bus_reset;
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input wire [3:0] i_bus_data_in;
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output wire [3:0] o_bus_data_out;
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output wire [0:0] o_bus_strobe;
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output wire [0:0] o_bus_cmd_data;
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`endif
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// clocks
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reg [1:0] clk_phase;
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@ -188,6 +195,7 @@ wire [0:0] ins_unconfig;
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saturn_alu m_alu (
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.i_clk (i_clk),
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.i_reset (i_reset),
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.i_clk_ph (clk_phase[1:0]),
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.i_cycle_ctr (cycle_ctr),
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.i_en_alu_dump (ck_alu_dump),
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.i_en_alu_prep (ck_alu_prep),
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@ -267,15 +275,17 @@ saturn_bus_ctrl m_bus_ctrl (
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// basic stuff
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.i_clk (i_clk),
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.i_reset (i_reset),
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.i_phase (o_phase),
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.i_cycle_ctr (cycle_ctr),
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.i_en_bus_send (ck_bus_send),
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.i_en_bus_recv (ck_bus_recv),
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.i_en_bus_ecmd (ck_bus_ecmd),
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.i_stalled (mem_ctrl_stall),
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.i_read_stall (dec_stalled),
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.o_stalled_by_bus (bus_stalls_core),
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.o_stall_alu (bus_stalls_core),
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//bus i/o
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.o_bus_reset (o_bus_reset),
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.i_bus_data (i_bus_data_in),
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.o_bus_data (o_bus_data_out),
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.o_bus_strobe (o_bus_strobe),
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@ -284,7 +294,7 @@ saturn_bus_ctrl m_bus_ctrl (
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// interface to the rest of the machine
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.i_alu_pc (reg_pc),
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.i_address (bus_address),
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.i_load_pc (bus_load_pc),
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.i_cmd_load_pc (bus_load_pc),
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.i_cmd_load_dp (bus_load_dp),
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.i_read_pc (bus_pc_read),
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.i_cmd_dp_read (bus_dp_read),
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@ -298,12 +308,6 @@ saturn_bus_ctrl m_bus_ctrl (
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reg [0:0] mem_ctrl_stall;
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wire [0:0] bus_stalls_core;
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// // bus to external modules
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// reg [3:0] bus_data_in;
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// wire [3:0] bus_data_out;
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// wire [0:0] bus_strobe;
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// wire [0:0] bus_cmd_data;
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// `define DEBUG_CLOCKS
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initial begin
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@ -390,7 +394,7 @@ always @(posedge i_clk) begin
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clock_end <= 0;
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cycle_ctr <= ~0;
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max_cycle <= 650;
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max_cycle <= 278;
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mem_ctrl_stall <= 0;
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`ifndef SIM
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@ -421,27 +425,170 @@ endmodule
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`ifdef SIM
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`include "def-buscmd.v"
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/******************************************************************************
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*
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* test rom
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*
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****************************************************************************/
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module test_rom (
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i_phase,
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i_reset,
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i_bus_data_in,
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o_bus_data_out,
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i_bus_strobe,
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i_bus_cmd_data
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);
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input wire [1:0] i_phase;
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input wire [0:0] i_reset;
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input wire [3:0] i_bus_data_in;
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output reg [3:0] o_bus_data_out;
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input wire [0:0] i_bus_strobe;
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input wire [0:0] i_bus_cmd_data;
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reg [31:0] cycles;
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`ifdef SIM
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`define ROMBITS 20
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`else
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`define ROMBITS 12
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`endif
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reg [3:0] rom [0:2**`ROMBITS-1];
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reg [19:0] local_pc;
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reg [19:0] local_dp;
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reg [3:0] last_bus_cmd;
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reg [2:0] addr_c;
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wire [0:0] s_load_pc;
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wire [0:0] s_load_dp;
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wire [0:0] s_pc_read;
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wire [0:0] s_dp_write;
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assign s_load_pc = (last_bus_cmd == `BUSCMD_LOAD_PC);
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assign s_load_dp = (last_bus_cmd == `BUSCMD_LOAD_DP);
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assign s_pc_read = (last_bus_cmd == `BUSCMD_PC_READ);
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assign s_dp_write = (last_bus_cmd == `BUSCMD_DP_WRITE);
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initial begin
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$readmemh("rom-gx-r.hex", rom, 0, 2**`ROMBITS-1);
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// $monitor("rst %b | strb %b | c/d %b | bus_i %h | bus_o %h | last %h | slpc %b | addr_c %0d | lpc %5h | ldp %5h",
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// i_reset, i_bus_strobe, i_bus_cmd_data, i_bus_data_in, o_bus_data_out,
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// last_bus_cmd, s_load_pc, addr_c, local_pc, local_dp);
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end
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always @(posedge i_bus_strobe) begin
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if (i_reset) begin
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cycles <= 0;
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last_bus_cmd <= `BUSCMD_NOP;
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addr_c <= 0;
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local_pc <= 0;
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local_dp <= 0;
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end
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if (!i_reset)
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cycles <= cycles + 1;
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if (!i_bus_cmd_data) begin
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$write("ROM %0d: [%d] COMMAND ", i_phase, cycles);
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case (i_bus_data_in)
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`BUSCMD_PC_READ: $write("PC_READ"); // 2
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`BUSCMD_DP_WRITE: $write("DP_WRITE"); // 5
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`BUSCMD_LOAD_PC: $write("LOAD_PC"); // 6
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`BUSCMD_LOAD_DP: $write("LOAD_DP"); // 7
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`BUSCMD_CONFIGURE: $write("CONFIGURE (ignore)"); // 8
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`BUSCMD_RESET: $write("RESET (ignore)"); // 15
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endcase
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$write(" (%h)\n", i_bus_data_in);
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last_bus_cmd <= i_bus_data_in;
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end
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// if (i_bus_cmd_data) begin
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// $display("BUS DATA %h", i_bus_data_in);
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// end
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if (i_bus_cmd_data && s_load_pc) begin
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$display("ROM %0d: [%d] ADDR_IN(%0d) %h => PC [%5h]", i_phase, cycles, addr_c, i_bus_data_in, local_pc);
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local_pc[addr_c*4+:4] <= i_bus_data_in;
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if (addr_c == 4) $display("ROM : [%d] auto PC_READ [%5h]", cycles, {i_bus_data_in, local_pc[15:0]});
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last_bus_cmd <= (addr_c == 4)?`BUSCMD_PC_READ:last_bus_cmd;
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addr_c <= (addr_c == 4)?0:addr_c + 1;
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end
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if (i_bus_cmd_data && s_load_dp) begin
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$display("ROM %0d: [%d] ADDR_IN(%0d) %h => DP [%5h]", i_phase, cycles, addr_c, i_bus_data_in, local_dp);
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local_dp[addr_c*4+:4] <= i_bus_data_in;
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if (addr_c == 4) $display("ROM : [%d] auto DP_READ [%5h]", cycles, {i_bus_data_in, local_dp[15:0]});
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last_bus_cmd <= (addr_c == 4)?`BUSCMD_DP_READ:last_bus_cmd;
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addr_c <= (addr_c == 4)?0:addr_c + 1;
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end
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if (i_bus_cmd_data && s_pc_read) begin
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o_bus_data_out <= rom[local_pc];
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$display("ROM %0d: [%d] %h <= PC_READ [%5h]", i_phase, cycles, rom[local_pc], local_pc);
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local_pc <= local_pc + 1;
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end
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if (i_bus_cmd_data && s_dp_write) begin
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$display("ROM %0d: [%d] %h => DP_WRITE [%5h] (ignored)", i_phase, cycles, i_bus_data_in, local_dp);
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end
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end
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endmodule
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/******************************************************************************
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*
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* test harness
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*
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****************************************************************************/
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module saturn_tb;
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saturn_core saturn (
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.i_clk (clk),
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.i_reset (reset),
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.o_halt (halt),
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.o_bus_reset (core_bus_reset),
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.i_bus_data_in (core_bus_data_in),
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.o_bus_data_out (core_bus_data_out),
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.o_bus_strobe (core_bus_strobe),
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.o_bus_cmd_data (core_bus_cmd_data)
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.o_bus_cmd_data (core_bus_cmd_data),
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.o_phase (core_phase)
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);
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test_rom rom (
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.i_phase (core_phase),
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.i_reset (core_bus_reset),
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.i_bus_data_in (core_bus_data_out),
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.o_bus_data_out (core_bus_data_in),
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.i_bus_strobe (core_bus_strobe),
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.i_bus_cmd_data (core_bus_cmd_data)
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);
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reg [0:0] clk;
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reg [0:0] reset;
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wire [0:0] halt;
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reg [3:0] core_bus_data_in;
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wire [0:0] core_bus_reset;
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wire [3:0] core_bus_data_in;
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wire [3:0] core_bus_data_out;
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wire [0:0] core_bus_strobe;
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wire [0:0] core_bus_cmd_data;
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wire [1:0] core_phase;
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always
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#10 clk = (clk === 1'b0);
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