diff --git a/saturn_bus_controller.v b/saturn_bus_controller.v
index 44b9094..d5e2b55 100644
--- a/saturn_bus_controller.v
+++ b/saturn_bus_controller.v
@@ -177,7 +177,10 @@ saturn_debugger debugger (
     .o_char_counter    (o_char_counter),
     .o_char_valid      (o_char_valid), 
     .o_char_send       (o_char_send),
-    .i_serial_busy     (i_serial_busy)
+    .i_serial_busy     (i_serial_busy),
+ 
+    .i_bus_nibble_in   (i_bus_nibble_in),
+    .i_bus_read_valid  (bus_read_valid)
 );
 
 wire [4:0] dbg_register;
@@ -223,6 +226,8 @@ initial begin
     bus_busy      = 1'b1;
 end
 
+wire [0:0] bus_read_valid = bus_clk_en && i_phases[2] && !bus_busy;
+
 /*
  * bus chronograms
  *
diff --git a/saturn_debugger.v b/saturn_debugger.v
index 320a506..50c1864 100644
--- a/saturn_debugger.v
+++ b/saturn_debugger.v
@@ -61,7 +61,10 @@ module saturn_debugger (
     o_char_counter,
     o_char_valid,
     o_char_send,
-    i_serial_busy
+    i_serial_busy,
+
+    i_bus_nibble_in,
+    i_bus_read_valid
 );
 
 input  wire [0:0]  i_clk;
@@ -104,6 +107,9 @@ output reg  [0:0]  o_char_valid;
 output reg  [0:0]  o_char_send;
 input  wire [0:0]  i_serial_busy;
 
+input  wire [3:0]  i_bus_nibble_in;
+input  wire [0:0]  i_bus_read_valid; 
+
 /**************************************************************************************************
  *
  * debugger process registers
@@ -528,8 +534,28 @@ always @(posedge i_clk) begin
         end
     end
 
+    /* not in debug mode, output the phase */
+    // if (i_clk_en && !o_debug_cycle) begin
+    //     o_char_send <= ~o_char_send;
+    //     case (i_phase)
+    //         2'd0: o_char_to_send <= "0";
+    //         2'd1: o_char_to_send <= "1";
+    //         2'd2: o_char_to_send <= "2";
+    //         2'd3: o_char_to_send <= "3";
+    //     endcase
+    //     o_char_valid <= 1'b1;
+    // end
+
+    if (i_bus_read_valid) begin
+        // $write("#### %c ####", hex[i_bus_nibble_in]); 
+        o_char_send    <= ~o_char_send;
+        o_char_to_send <= hex[i_bus_nibble_in];
+        o_char_valid   <= 1'b1;
+    end
+ 
     /* clear the char clock enable */
-    if (write_out && o_char_valid && i_serial_busy) begin
+    // if (write_out && o_char_valid && i_serial_busy) begin
+    if (o_char_valid) begin
         o_char_valid <= 1'b0;
     end
 
diff --git a/saturn_hp48gx_rom.v b/saturn_hp48gx_rom.v
index a7fe348..27e52a6 100644
--- a/saturn_hp48gx_rom.v
+++ b/saturn_hp48gx_rom.v
@@ -25,7 +25,7 @@
 `ifdef SIM
 `define ROMBITS 20
 `else
-`define ROMBITS 13
+`define ROMBITS 16
 `endif
 
 module saturn_hp48gx_rom (
diff --git a/saturn_serial.v b/saturn_serial.v
index 3f54e3e..9ae40d5 100644
--- a/saturn_serial.v
+++ b/saturn_serial.v
@@ -77,6 +77,7 @@ always @(posedge i_clk) begin
 
     // $display("%0d", bit_delay);
     if (i_char_valid && !o_serial_busy) begin
+        // $write("%c", i_char_to_send);
         // $display("serial storing char %c", i_char_to_send);
         clocking_reg <= 11'b0;
         data_reg     <= { 1'b1, i_char_to_send, 1'b0 };
diff --git a/saturn_top.v b/saturn_top.v
index c3cddcc..3b9f7a5 100644
--- a/saturn_top.v
+++ b/saturn_top.v
@@ -66,19 +66,25 @@ end
 always 
     #10 clk = (clk === 1'b0);
 
+reg [3:0] delay;
 reg [0:0] clk_en;
 reg [7:0] test;
 
 initial begin
-    clk_en = 1'b1;
+    delay  = 4'b0001;
+    clk_en = 1'b0;
     test   = 8'b1;
 end
 
 always @(posedge clk) begin
     test   <= {test[6:0], test[7]};
 
+    delay  <= { delay[2:0], delay[3]};
+    if (delay[0]) clk_en <= 1'b1;
+    if (clk_en) clk_en <= 1'b0;
+
     if (reset) begin
-        clk_en <= 1'b1;
+        clk_en <= 1'b0;
         test   <= 8'b1;
     end
 end
@@ -171,24 +177,25 @@ end
 
 always @(posedge clk_25mhz) begin
     delay <= delay + 26'b1;
-    led    <= char_counter[7:0];
+    // led    <= char_counter[7:0];
     if (delay[`TEST_BIT]) begin
         delay  <= `DELAY_START;
         reset  <= btn[1];
         clk2   <= ~clk2;
     end
-    led[7] <= clk2;
+    led[7] <= halt;
     led[6] <= char_send;
+    led[5] <= serial_busy;
 
     if (clk2 && !halt) begin
         clk_en <= 1'b1;
-        led[5] <= ~led[5];
     end
 
     if (clk_en) begin
         clk_en <= 1'b0;
-        led[4] <= ~led[4];
     end
+    led[3] <= clk_en;
+    // led[1:0] <= phase;
 end
 
 endmodule