Miroirs/hp-saturn
1
0
Fork 0
mirror of https://github.com/sxpert/hp-saturn synced 2025-01-19 10:26:58 +01:00
Code Issues Projects Releases Packages Wiki Activity

add some ifdefs to hide the various display statements

Browse source
This commit is contained in:
Raphael Jacquot 2019-02-04 16:49:11 +01:00
parent 5d8fcd41fa
commit 610647d724
1 changed files with 106 additions and 54 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

160
saturn_core.v
View file

@ -194,6 +194,7 @@ always @(posedge clk)
//-------------------------------------------------------------------------------------------------- //--------------------------------------------------------------------------------------------------
// display registers // display registers
`ifdef SIM
always @(posedge clk) always @(posedge clk)
if ((runstate == RUN_START) & (~reset)) if ((runstate == RUN_START) & (~reset))
begin begin
@ -207,7 +208,7 @@ always @(posedge clk)
$display("D0: %h D1: %h R4: %h RSTK1: %5h", D0, D1, R4, RSTK[1]); $display("D0: %h D1: %h R4: %h RSTK1: %5h", D0, D1, R4, RSTK[1]);
$display(" RSTK0: %5h", RSTK[0]); $display(" RSTK0: %5h", RSTK[0]);
end end
`endif
//-------------------------------------------------------------------------------------------------- //--------------------------------------------------------------------------------------------------
// //
@ -271,7 +272,9 @@ always @(posedge clk)
//4'ha : decstate <= DECODE_A_FS; //4'ha : decstate <= DECODE_A_FS;
default: default:
begin begin
`ifdef SIM
$display("%05h nibble %h => unimplemented", saved_PC, nibble); $display("%05h nibble %h => unimplemented", saved_PC, nibble);
`endif
halt <= 1; halt <= 1;
end end
endcase endcase
@ -455,13 +458,17 @@ always @(posedge clk)
READ_ROM_VAL: READ_ROM_VAL:
begin begin
P <= nibble; P <= nibble;
`ifdef SIM
$display("%05h P=\t%h", saved_PC, nibble); $display("%05h P=\t%h", saved_PC, nibble);
`endif
runstate <= RUN_START; runstate <= RUN_START;
decstate <= DECODE_START; decstate <= DECODE_START;
end end
default: default:
begin begin
`ifdef SIM
$display("runstate %h", runstate); $display("runstate %h", runstate);
`endif
halt <= 1; halt <= 1;
end end
endcase endcase
@ -523,13 +530,17 @@ always @(posedge clk)
jump_offset <= 0; jump_offset <= 0;
load_cnt <= 2; load_cnt <= 2;
load_ctr <= 0; load_ctr <= 0;
`ifdef SIM
$write("%5h GOTO\t", saved_PC); $write("%5h GOTO\t", saved_PC);
`endif
end end
READ_ROM_STA, READ_ROM_CLK, READ_ROM_STR: ; READ_ROM_STA, READ_ROM_CLK, READ_ROM_STR: ;
READ_ROM_VAL: READ_ROM_VAL:
begin begin
jump_offset[load_ctr*4+:4] <= nibble; jump_offset[load_ctr*4+:4] <= nibble;
`ifdef SIM
$write("%1h", nibble); $write("%1h", nibble);
`endif
if (load_ctr == load_cnt) runstate <= RUN_EXEC; if (load_ctr == load_cnt) runstate <= RUN_EXEC;
else else
begin begin
@ -539,14 +550,17 @@ always @(posedge clk)
end end
RUN_EXEC: RUN_EXEC:
begin begin
`ifdef SIM
$display("\t=> %05h", jump_base + jump_offset); $display("\t=> %05h", jump_base + jump_offset);
PC <= jump_base + jump_offset; `endif PC <= jump_base + jump_offset;
runstate <= RUN_START; runstate <= RUN_START;
decstate <= DECODE_START; decstate <= DECODE_START;
end end
default: default:
begin begin
`ifdef SIM
$display("runstate %h", runstate); $display("runstate %h", runstate);
`endif
halt <= 1; halt <= 1;
end end
endcase endcase
@ -563,22 +577,29 @@ always @(posedge clk)
RUN_DECODE: runstate <= READ_ROM_STA; RUN_DECODE: runstate <= READ_ROM_STA;
READ_ROM_STA, READ_ROM_CLK, READ_ROM_STR: ; READ_ROM_STA, READ_ROM_CLK, READ_ROM_STR: ;
READ_ROM_VAL: READ_ROM_VAL:
case (nibble) begin
//4'h0: decode_80(); case (nibble)
//4'h2: decode_82(); //4'h0: decode_80();
//4'h4: inst_st_eq_0_n(); //4'h2: decode_82();
//4'h5: inst_st_eq_1_n(); //4'h4: inst_st_eq_0_n();
4'hd: decstate <= DECODE_GOVLNG; //4'h5: inst_st_eq_1_n();
//4'hf: decstate <= DECODE_GOSBVL; 4'hd: decstate <= DECODE_GOVLNG;
default: //4'hf: decstate <= DECODE_GOSBVL;
begin default:
$display("unhandled instruction prefix 8%h", nibble); begin
halt <= 1; `ifdef SIM
end $display("unhandled instruction prefix 8%h", nibble);
endcase `endif
halt <= 1;
end
endcase
runstate <= RUN_DECODE;
end
default: default:
begin begin
`ifdef SIM
$display("runstate %h", runstate); $display("runstate %h", runstate);
`endif
halt <= 1; halt <= 1;
end end
endcase endcase
@ -666,7 +687,30 @@ task decode_82;
end end
endcase endcase
endtask endtask
*/
/******************************************************************************
* ---------- field -----------
* A B fs d
* ----------------------------
* 140 148 150a 158x DAT0=A field
* 141 149 151a 159x DAT1=A field
* 142 14A 152a 15Ax A=DAT0 field
* 143 14B 153a 15Bx A=DAT1 field
* 144 14C 154a 15Cx DAT0=C field
* 145 14D 155a 15Dx DAT1=C field
* 146 14E 156a 15Ex C=DAT0 field
* 147 14F 157a 15Fx C=DAT1 field
*
* fs: P WP XS X S M B W
* a: 0 1 2 3 4 5 6 7
*
* x = d - 1 x = n - 1
*/
/*
// 84n ST=0 n // 84n ST=0 n
task inst_st_eq_0_n; task inst_st_eq_0_n;
case (decstate ) case (decstate )
@ -712,52 +756,60 @@ endtask
* two for the price of one... * two for the price of one...
*/ */
/* always @(posedge clk)
task inst_govlng_gosbvl; if ((decstate == DECODE_GOVLNG) | (decstate == DECODE_GOSBVL))
case (decstate ) case (runstate)
DECODE_8X: RUN_DECODE:
begin
read_state <= READ_START;
jump_base <= 0;
load_cnt <= 4;
load_ctr <= 0;
case (nibble)
4'hD:
begin
decstate <= DECODE_GOVLNG;
$write("%5h GOVLNG\t", saved_PC);
end
4'hF:
begin
decstate <= DECODE_GOSBVL;
rstk_ptr <= rstk_ptr + 1;
$write("%5h GOSBVL\t", saved_PC);
end
endcase
end
DECODE_GOVLNG, DECODE_GOSBVL:
if (read_state != READ_VALID) read_rom();
else
begin begin
jump_base[load_ctr*4+:4] = nibble; jump_base <= 0;
$write("%1h", nibble); load_cnt <= 4;
if (load_ctr == load_cnt) load_ctr <= 0;
begin `ifdef SIM
$display("\t=> %5h", jump_base); case (decstate)
if (decstate == DECODE_GOSBVL) DECODE_GOVLNG: $write("%5h GOVLNG\t", saved_PC);
RSTK[rstk_ptr] <= PC; DECODE_GOSBVL: $write("%5h GOSBVL\t", saved_PC);
PC <= jump_base; endcase
end_decode(); `endif
end if (decstate == DECODE_GOSBVL)
rstk_ptr <= rstk_ptr + 1;
runstate <= READ_ROM_STA;
end
READ_ROM_STA, READ_ROM_CLK, READ_ROM_STR: ;
READ_ROM_VAL:
begin
//$display("decstate %h | nibble %h", decstate, nibble);
jump_base[load_ctr*4+:4] = nibble;
`ifdef SIM
$write("%1h", nibble);
`endif
if (load_ctr == load_cnt) runstate <= RUN_EXEC;
else else
begin begin
load_ctr <= load_ctr + 1; load_ctr <= load_ctr + 1;
read_state <= READ_START; runstate <= READ_ROM_STA;
end end
end end
endcase RUN_EXEC:
endtask begin
`ifdef SIM
$display("\t=> %5h", jump_base);
`endif
if (decstate == DECODE_GOSBVL)
RSTK[rstk_ptr] <= PC;
PC <= jump_base;
runstate <= RUN_START;
decstate <= DECODE_START;
end
default:
begin
`ifdef SIM
$display("decstate %h", decstate);
`endif
halt <= 1;
end
endcase
/*
task decode_a; task decode_a;
case (decstate) case (decstate)
DECODE_START: DECODE_START: