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try replacing all ifs with a case... yosys blows up too

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This commit is contained in:
Raphael Jacquot 2019-02-07 11:54:11 +01:00
parent 0940b198d3
commit 4800c6f241
9 changed files with 10842 additions and 74 deletions
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2
compile
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@ -5,5 +5,5 @@
#yosys -p "synth_ecp5 -top saturn_core -json saturn_core.json" saturn_core.v
yosys saturn_core.ys
yosys saturn_core.ESP5.ys
nextpnr-ecp5 --gui --85k --speed 6 --freq 5 --lpf ulx3s_v20.lpf --textcfg empty_lfe5u-85f.config --json saturn_core.json --save saturn_core.ecp5

10683
demo.blif Normal file
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File diff suppressed because it is too large Load diff

2
hp48_io_ram.v
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@ -141,7 +141,7 @@ always @(negedge clk)
// test if write can be done
if (io_ram_active)
begin
io_ram[data_ptr - base_addr] <= nibble_in;
io_ram[data_ptr[5:0] - base_addr[5:0]] <= nibble_in;
`ifdef SIM
$display("io_ram: DP_WRITE %5h %h | OK", data_ptr, nibble_in);
`endif

7
ico Executable file
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@ -0,0 +1,7 @@
#!/bin/bash
#
# licence: GPLv3 or later
#
yosys saturn_core.ICE40.ys
#nextpnr-ecp5 --gui --85k --speed 6 --freq 5 --lpf ulx3s_v20.lpf --textcfg empty_lfe5u-85f.config --json saturn_core.json --save saturn_core.ecp5

48
icoboard.pcf Normal file
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@ -0,0 +1,48 @@
#
# Copyright (c) 2017 Joel Holdsworth <joel@airwebreathe.org.uk>
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# 3. Neither the name of copyright holder nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
set_io clk_100mhz R9
set_io pmod1_1 D8
set_io pmod1_2 B9
set_io pmod1_3 B10
set_io pmod1_4 B11
set_io pmod1_7 B8
set_io pmod1_8 A9
set_io pmod1_9 A10
set_io pmod1_10 A11
set_io pmod2_7 B7
set_io pmod2_8 B6
set_io pmod2_9 B3
set_io pmod2_10 B5
set_io rpi_sck H11
set_io rpi_cs D4
set_io rpi_mosi A6

2
saturn_core.ESP5.ys Normal file
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@ -0,0 +1,2 @@
read_verilog -I. saturn_core.v
synth_ecp5 -top saturn_core -json saturn_core.json

2
saturn_core.ICE40.ys Normal file
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@ -0,0 +1,2 @@
read_verilog -I. saturn_core.v
synth_ice40 -blif demo.blif

148
saturn_core.v
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@ -54,7 +54,7 @@ module saturn_core (
input reset,
output halt,
output [3:0] runstate,
output [15:0] decstate
output [4:0] decstate
);
`else
module saturn_core (
@ -73,58 +73,52 @@ assign reset = btn[1];
`endif
// led display states
localparam REGDMP_HEX = 8'h00;
// bus commands
// localparam BUSCMD_DP_WRITE = `C_BUSCMD_DP_WRITE;
// localparam BUSCMD_CONFIGURE = `C_BUSCMD_CONFIGURE;
localparam REGDMP_HEX = 0;
// instruction decoder states
localparam DECODE_START = 16'h0000;
localparam DECODE_START = 0; // x
localparam DECODE_0 = 16'h0001;
localparam DECODE_0X = 16'h0002;
localparam DECODE_0 = 1; // 0
localparam DECODE_0X = 2; // 0x
localparam DECODE_RTNCC = 16'h0300;
localparam DECODE_SETHEX = 16'h0400;
localparam DECODE_SETDEC = 16'h0500;
localparam DECODE_RTNCC = 3; // 03
localparam DECODE_SETHEX = 4; // 04
localparam DECODE_SETDEC = 5; // 05
localparam DECODE_1 = 16'h0010;
localparam DECODE_1X = 16'h0011;
localparam DECODE_14 = 16'h0410;
localparam DECODE_15 = 16'h0510;
localparam DECODE_MEMACCESS = 16'h0411;
localparam DECODE_D0_EQ_5N = 16'h0b10;
localparam DECODE_1 = 6; // 1
localparam DECODE_1X = 7; // 1x
localparam DECODE_14 = 8; // 14
localparam DECODE_15 = 9; // 15
localparam DECODE_MEMACCESS = 10; // 1[45]x[y]
localparam DECODE_D0_EQ_5N = 11; // 1Bzyxwv
localparam DECODE_P_EQ = 16'h0020;
localparam DECODE_P_EQ = 12; // 2n
localparam DECODE_LC_LEN = 16'h0030;
localparam DECODE_LC = 16'h0031;
localparam DECODE_LC_LEN = 13; // 3n
localparam DECODE_LC = 14; // 3n{xxxxxxxxxxxxxxxx}
localparam DECODE_GOTO = 16'h0060;
localparam DECODE_GOTO = 15; // 6zyx
localparam DECODE_8 = 16'h0080;
localparam DECODE_8X = 16'h0081;
localparam DECODE_80 = 16'h0082;
localparam DECODE_8 = 16; // 8
localparam DECODE_8X = 17; // 8x
localparam DECODE_80 = 18; // 80
localparam DECODE_CONFIG = 16'h5080;
localparam DECODE_RESET = 16'hA080;
localparam DECODE_CONFIG = 19; // 805
localparam DECODE_RESET = 20; // 80A
localparam DECODE_C_EQ_P_N = 16'hC080;
localparam DECODE_C_EQ_P_N = 21; // 80Cn
localparam DECODE_82 = 16'h0280;
localparam DECODE_82 = 22; // 82
localparam DECODE_ST_EQ_0_N = 16'h0480;
localparam DECODE_ST_EQ_1_N = 16'h0580;
localparam DECODE_ST_EQ_0_N = 23; // 84n
localparam DECODE_ST_EQ_1_N = 24; // 85n
localparam DECODE_GOVLNG = 16'h0d80;
localparam DECODE_GOSBVL = 16'h0f80;
localparam DECODE_GOVLNG = 25; // 8Dzyxwv
localparam DECODE_GOSBVL = 26; // 8Fzyxwv
localparam DECODE_A = 16'h00a0;
localparam DECODE_A_FS = 16'h00a1;
localparam DECODE_A = 27; // A
localparam DECODE_A_FS = 28; // A()
// status registers constants
@ -153,8 +147,8 @@ localparam T_FIELD_A = 15;
// state machine stuff
reg halt;
reg [3:0] runstate;
reg [15:0] decstate;
reg [7:0] regdump;
reg [4:0] decstate;
reg [3:0] regdump;
// bus access
reg [19:0] bus_address;
@ -427,7 +421,10 @@ begin
*
*/
if (decstate == DECODE_0)
case (decstate)
//if (decstate == DECODE_0)
DECODE_0:
case (runstate)
`RUN_DECODE: runstate <= `INSTR_START;
`INSTR_START, `INSTR_STROBE: begin end
@ -460,7 +457,8 @@ begin
*
*/
if (decstate == DECODE_RTNCC)
//if (decstate == DECODE_RTNCC)
DECODE_RTNCC:
begin
Carry <= 0;
PC <= RSTK[rstk_ptr];
@ -480,7 +478,8 @@ begin
*
*/
if (decstate == DECODE_SETHEX)
//if (decstate == DECODE_SETHEX)
DECODE_SETHEX:
begin
hex_dec <= HEX;
`ifdef SIM
@ -496,7 +495,8 @@ begin
*
*/
if (decstate == DECODE_SETDEC)
//if (decstate == DECODE_SETDEC)
DECODE_SETDEC:
begin
hex_dec <= DEC;
`ifdef SIM
@ -512,7 +512,8 @@ begin
*
*/
if (decstate == DECODE_1)
//if (decstate == DECODE_1)
DECODE_1:
case (runstate)
`RUN_DECODE: runstate <= `INSTR_START;
`INSTR_START, `INSTR_STROBE: begin end
@ -563,7 +564,8 @@ begin
*
*/
if ((decstate == DECODE_14)|(decstate == DECODE_15))
//if ((decstate == DECODE_14)|(decstate == DECODE_15))
DECODE_14, DECODE_15:
case (runstate)
`RUN_DECODE: runstate <= `INSTR_START;
`INSTR_START, `INSTR_STROBE: begin end
@ -599,7 +601,8 @@ begin
end
endcase
if (decstate == DECODE_MEMACCESS)
//if (decstate == DECODE_MEMACCESS)
DECODE_MEMACCESS:
case (runstate)
`RUN_EXEC:
begin
@ -686,7 +689,8 @@ begin
*
*/
if (decstate == DECODE_D0_EQ_5N)
//if (decstate == DECODE_D0_EQ_5N)
DECODE_D0_EQ_5N:
case (runstate)
`RUN_DECODE:
begin
@ -733,7 +737,8 @@ begin
*
*/
if (decstate == DECODE_P_EQ)
//if (decstate == DECODE_P_EQ)
DECODE_P_EQ:
case (runstate)
`RUN_DECODE: runstate <= `INSTR_START;
`INSTR_START, `INSTR_STROBE: begin end
@ -762,7 +767,8 @@ begin
*
*/
if ((decstate == DECODE_LC_LEN) | (decstate == DECODE_LC))
//if ((decstate == DECODE_LC_LEN) | (decstate == DECODE_LC))
DECODE_LC_LEN, DECODE_LC:
case (runstate)
`RUN_DECODE: runstate <= `INSTR_START;
`INSTR_START, `INSTR_STROBE: begin end
@ -822,7 +828,8 @@ begin
*
*/
if (decstate == DECODE_GOTO)
//if (decstate == DECODE_GOTO)
DECODE_GOTO:
case (runstate)
`RUN_DECODE:
begin
@ -872,7 +879,8 @@ begin
*
*/
if (decstate == DECODE_8)
//if (decstate == DECODE_8)
DECODE_8:
case (runstate)
`RUN_DECODE: runstate <= `INSTR_START;
`INSTR_START, `INSTR_STROBE: begin end
@ -910,7 +918,8 @@ begin
*
*/
if (decstate == DECODE_80)
//if (decstate == DECODE_80)
DECODE_80:
case (runstate)
`RUN_DECODE: runstate <= `INSTR_START;
`INSTR_START, `INSTR_STROBE: begin end
@ -947,7 +956,9 @@ begin
*
*/
if ((decstate == DECODE_CONFIG) & (runstate == `RUN_DECODE))
//if ((decstate == DECODE_CONFIG) & (runstate == `RUN_DECODE))
DECODE_CONFIG:
if (runstate == `RUN_DECODE)
begin
`ifdef SIM
$display("%05h CONFIG\t\t\t<= NOT IMPLEMENTED YET", saved_PC);
@ -962,7 +973,9 @@ begin
*
*/
if ((decstate == DECODE_RESET) & (runstate == `RUN_DECODE))
//if ((decstate == DECODE_RESET) & (runstate == `RUN_DECODE))
DECODE_RESET:
if (runstate == `RUN_DECODE)
begin
`ifdef SIM
$display("%05h RESET\t\t\t<= NOT IMPLEMENTED YET", saved_PC);
@ -977,7 +990,8 @@ begin
*
*/
if (decstate == DECODE_C_EQ_P_N)
//if (decstate == DECODE_C_EQ_P_N)
DECODE_C_EQ_P_N:
case (runstate)
`RUN_DECODE: runstate <= `INSTR_START;
`INSTR_START, `INSTR_STROBE: begin end
@ -1007,7 +1021,8 @@ begin
*
*/
if (decstate == DECODE_82)
//if (decstate == DECODE_82)
DECODE_82:
case (runstate)
`RUN_DECODE: runstate <= `INSTR_START;
`INSTR_START, `INSTR_STROBE: begin end
@ -1041,7 +1056,8 @@ begin
* 85n ST=1 n
*/
if ((decstate == DECODE_ST_EQ_0_N) | (decstate == DECODE_ST_EQ_1_N))
//if ((decstate == DECODE_ST_EQ_0_N) | (decstate == DECODE_ST_EQ_1_N))
DECODE_ST_EQ_0_N, DECODE_ST_EQ_1_N:
case (runstate)
`RUN_DECODE: runstate <= `INSTR_START;
`INSTR_START, `INSTR_STROBE: begin end
@ -1081,7 +1097,8 @@ begin
* two for the price of one...
*/
if ((decstate == DECODE_GOVLNG) | (decstate == DECODE_GOSBVL))
//if ((decstate == DECODE_GOVLNG) | (decstate == DECODE_GOSBVL))
DECODE_GOVLNG, DECODE_GOSBVL:
case (runstate)
`RUN_DECODE:
begin
@ -1137,7 +1154,8 @@ begin
*
*/
if ((decstate == DECODE_A)|(decstate == DECODE_A_FS))
//if ((decstate == DECODE_A)|(decstate == DECODE_A_FS))
DECODE_A, DECODE_A_FS:
case (runstate)
`RUN_DECODE: runstate <= `INSTR_START;
`INSTR_START, `INSTR_STROBE: begin end
@ -1197,6 +1215,16 @@ begin
end
endcase
default:
begin
`ifdef SIM
$display("decstate %h not handled", decstate);
`endif
//halt <= 1;
end
endcase
/**************************************************************************************************
*
* Dump all registers to leds, one piece at a time
@ -1227,7 +1255,7 @@ reg clk;
reg reset;
wire halt;
wire [3:0] runstate;
wire [15:0] decstate;
wire [4:0] decstate;
saturn_core saturn (
.clk (clk),

2
saturn_core.ys
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@ -1,2 +0,0 @@
read_verilog -I. saturn_core.v
synth_ecp5 -top saturn_core -json saturn_core.json