Miroirs/hp-saturn
1
0
Fork 0
mirror of https://github.com/sxpert/hp-saturn synced 2024-12-26 09:58:09 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions

more stuff implemented

Browse source
This commit is contained in:
Raphael Jacquot 2019-02-10 09:02:24 +01:00
parent 71b2349831
commit 4594dec086
11 changed files with 184 additions and 71 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

14
decstates.v
View file

@ -27,10 +27,15 @@
`define DEC_80X 12'h801 // 80X
`define DEC_CONFIG 12'h805 // 805
`define DEC_RESET 12'h80A // 80A
`define DEC_C_EQ_P_N 12'h80C // 80Cm
`define DEC_C_EQ_P_N 12'h80C // 80Cn C=P n
`define DEC_P_EQ_C_N 12'h80D // 80Dn P=C n
`define DEC_82X_CLRHST 12'h820 // 82X
`define DEC_ST_EQ_0_N 12'h840 // 84n
`define DEC_ST_EQ_1_N 12'h850 // 85n
`define DEC_ST_EQ_0_N 12'h840 // 84n ST=0 n
`define DEC_ST_EQ_1_N 12'h850 // 85n ST=1 n
`define DEC_TEST_ST_EQ_0_N 12'h860 // 86n ?ST=0 n
`define DEC_TEST_ST_EQ_1_N 12'h870 // 87n ?ST=1 n
`define DEC_TEST_P_NEQ_N 12'h880 // 88n ?P# n
`define DEC_TEST_P_EQ_N 12'h890 // 89n ?P= n
`define DEC_8AX 12'h8A0 // 8Ax
`define DEC_GOVLNG 12'h8D0 // 8D
`define DEC_GOVLNG_LOOP 12'h8D1 // 8D[x]
@ -45,6 +50,7 @@
`define DEC_CX 12'hC00 // Cx
`define DEC_DX 12'hD00 // Dx
`define DEC_FX 12'hF00 // Fx
`define DEC_TEST_GO 12'hFFF // GOYES / RTNYES
`define DEC_TEST_GO 12'hFFE // GOYES / RTNYES nibble 1
`define DEC_TEST_GO_1 12'hFFF // GOYES / RTNYES nibble 2
`endif

2
opcodes/1[45]_memaccess.v
View file

@ -108,7 +108,7 @@ end
if ((t_cnt==t_ctr) &
(((t_dir == `T_DIR_IN) & (decstate == `DEC_MEMAXX)) |
(((t_dir == `T_DIR_IN) & (decstate == `DEC_MEMAXX)&(next_cycle!=`BUSCMD_LOAD_DP)) |
((t_dir == `T_DIR_OUT) & (decstate == `DEC_MEMAXX_END)))) begin
$display("---------------------------- DEC_MEMAXX_END -------------------------------");
decstate <= `DEC_START;

18
opcodes/805_CONFIG.v
View file

@ -1,18 +0,0 @@
/******************************************************************************
* 805 CONFIG
*
*
*/
`include "decstates.v"
`include "bus_commands.v"
begin
add_out <= C[19:0];
next_cycle <= `BUSCMD_CONFIGURE;
decstate <= `DEC_START;
`ifdef SIM
$display("%05h CONFIG", inst_start_PC);
`endif
end

8
opcodes/80Cn_C_EQ_P_n.v → opcodes/80[CD]n_C_and_P_n.v
View file

@ -13,3 +13,11 @@
$display("%05h C=P\t%h", inst_start_PC, nb_in);
`endif
end
`DEC_P_EQ_C_N: begin
P <= C[nb_in*4+:4];
decstate <= `DEC_START;
`ifdef SIM
$display("%05h P=C\t%h", inst_start_PC, nb_in);
`endif
end

23
opcodes/80x.v
View file

@ -6,14 +6,27 @@
*/
`include "decstates.v"
`include "bus_commands.v"
`DEC_80X: begin
case (nb_in)
4'h5:
`include "opcodes/805_CONFIG.v"
4'ha:
`include "opcodes/80A_RESET.v"
4'hc: decstate <= `DEC_C_EQ_P_N;
4'h5: begin
add_out <= C[19:0];
next_cycle <= `BUSCMD_CONFIGURE;
decstate <= `DEC_START;
`ifdef SIM
$display("%05h CONFIG", inst_start_PC);
`endif
end
4'hA: begin
next_cycle <= `BUSCMD_RESET;
decstate <= `DEC_START;
`ifdef SIM
$display("%05h RESET", inst_start_PC);
`endif
end
4'hC: decstate <= `DEC_C_EQ_P_N;
4'hD: decstate <= `DEC_P_EQ_C_N;
default: begin
$display("ERROR : DEC_80X");
decode_error <= 1;

14
opcodes/8[45]n_ST_EQ_[01]_n.v → opcodes/8[4567]n_work_test_ST.v
View file

@ -19,3 +19,17 @@ end
$display("%05h ST=1\t%h", inst_start_PC, nb_in);
`endif
end
`DEC_TEST_ST_EQ_0_N: begin
Carry <= (!ST[nb_in]);
decstate <= `DEC_TEST_GO;
`ifdef SIM
$display("%05h ?ST=0\t%h", inst_start_PC, nb_in);
`endif
end
`DEC_TEST_ST_EQ_1_N: begin
Carry <= (ST[nb_in]);
decstate <= `DEC_TEST_GO;
`ifdef SIM
$display("%05h ?ST=1\t%h", inst_start_PC, nb_in);
`endif
end

20
opcodes/8[89]n_test_P.v Normal file
View file

@ -0,0 +1,20 @@
/******************************************************************************
* 88n ?P# n
* 89n ?P= n
*
*/
`DEC_TEST_P_NEQ_N: begin
Carry <= !(P == nb_in);
decstate <= `DEC_TEST_GO;
`ifdef SIM
$display("%5h ?P#\t\t%h", inst_start_PC, nb_in);
`endif
end
`DEC_TEST_P_EQ_N: begin
Carry <= (P == nb_in);
decstate <= `DEC_TEST_GO;
`ifdef SIM
$display("%5h ?P=\t\t%h", inst_start_PC, nb_in);
`endif
end

4
opcodes/8x.v
View file

@ -13,6 +13,10 @@
4'h2: decstate <= `DEC_82X_CLRHST;
4'h4: decstate <= `DEC_ST_EQ_0_N;
4'h5: decstate <= `DEC_ST_EQ_1_N;
4'h6: decstate <= `DEC_TEST_ST_EQ_0_N;
4'h7: decstate <= `DEC_TEST_ST_EQ_1_N;
4'h8: decstate <= `DEC_TEST_P_NEQ_N;
4'h9: decstate <= `DEC_TEST_P_EQ_N;
4'hA: decstate <= `DEC_8AX;
4'hD: decstate <= `DEC_GOVLNG;
4'hF: decstate <= `DEC_GOSBVL;

22
opcodes/Fx.v
View file

@ -29,6 +29,28 @@
endcase
if (!hex_dec) $display("\tA");
else $display("\tA\t\t\t <=== DEC MODE NOT IMPLEMENTED");
`endif
end
4'hC, 4'hD, 4'hE, 4'hF: begin
if (!hex_dec) begin
case (nb_in)
4'hC: {Carry, A[19:0]} <= - A[19:0] - 1;
4'hD: {Carry, B[19:0]} <= - B[19:0] - 1;
4'hE: {Carry, C[19:0]} <= - C[19:0] - 1;
4'hF: {Carry, D[19:0]} <= - D[19:0] - 1;
endcase
decstate <= `DEC_START;
end
`ifdef SIM
$write("%5h ", inst_start_PC);
case (nb_in)
4'h8: $write("A=-A-1");
4'h8: $write("B=-B-1");
4'h8: $write("C=-C-1");
4'h8: $write("D=-D-1");
endcase
if (!hex_dec) $display("\tA");
else $display("\tA\t\t\t <=== DEC MODE NOT IMPLEMENTED");
`endif
end
default: begin

42
opcodes/xx_RTNYES_GOYES.v Normal file
View file

@ -0,0 +1,42 @@
/******************************************************************************
* xx
* RTNYES or GOYES
*
*/
`include "decstates.v"
`DEC_TEST_GO: begin
jump_base <= PC;
jump_offset <= {{16{1'b0}},nb_in};
decstate <= `DEC_TEST_GO_1;
end
`DEC_TEST_GO_1: begin
$display("DEC_TEST_GO_1 opcode %h | base %h | offset %h",
{nb_in, jump_offset[3:0]}, jump_base,
{{12{nb_in[3]}},nb_in,jump_offset[3:0]});
if (Carry) begin
case ({nb_in, jump_offset[3:0]})
8'h00: begin // RTNYES
new_PC <= RSTK[rstk_ptr];
RSTK[rstk_ptr] <= 0;
rstk_ptr <= rstk_ptr - 1;
next_cycle <= `BUSCMD_LOAD_PC;
end
default: begin // GOYES
new_PC <= jump_base + {{12{nb_in[3]}},nb_in,jump_offset[3:0]};
next_cycle <= `BUSCMD_LOAD_PC;
end
endcase
end
`ifdef SIM
$write("%5h ", jump_base);
case ({nb_in, jump_offset[3:0]})
8'h00: $display("RTNYES");
default: $display ("GOYES\t%2h\t=> %5h", {nb_in, jump_offset[3:0]},
jump_base + {{12{nb_in[3]}},nb_in,jump_offset[3:0]});
endcase
`endif
decstate <= `DEC_START;
end

8
saturn_core.v
View file

@ -326,7 +326,7 @@ always @(posedge ph2)
end
always @(posedge ph3) begin
if (cycle_ctr == 240)
if (cycle_ctr == 333)
debug_stop <= 1;
end
@ -397,9 +397,10 @@ always @(posedge dec_strobe) begin
`include "opcodes/7xxx_GOSUB.v"
`include "opcodes/8x.v"
`include "opcodes/80x.v"
`include "opcodes/80Cn_C_EQ_P_n.v"
`include "opcodes/80[CD]n_C_and_P_n.v"
`include "opcodes/82x_CLRHST.v"
`include "opcodes/8[45]n_ST_EQ_[01]_n.v"
`include "opcodes/8[4567]n_work_test_ST.v"
`include "opcodes/8[89]n_test_P.v"
`include "opcodes/8Ax_test_[n]eq_A.v"
`include "opcodes/8[DF]xxxxx_GO.v"
`include "opcodes/A[ab]x.v"
@ -407,6 +408,7 @@ always @(posedge dec_strobe) begin
`include "opcodes/Cx.v"
`include "opcodes/Dx_regs_field_A.v"
`include "opcodes/Fx.v"
`include "opcodes/xx_RTNYES_GOYES.v"
default: begin
$display("ERROR : GENERAL");
decode_error <= 1;