diff --git a/history.txt b/history.txt
index fe9f2dc..9451f58 100644
--- a/history.txt
+++ b/history.txt
@@ -42,3 +42,4 @@ second delay is posedge $glbnet$clk -> <async>
 2019-02-17 22:31    1573         77.32MHz   32.91ns     12.77ns     10265    70.53MHz   17.35ns     4.13ns
 2019-02-17 22:48    1067         69.94MHz   32.87ns     12.77ns      6427    74.33MHz   17.71ns     3.96ns 
 2019-02-17 23:04    1158         64.11MHz   37.87ns     12.77ns      7149    66.74MHz   19.03ns     4.06ns
+2019-02-18 07:45    1128         74.65MHz   36.49ns     13.73ns      7586    75.72MHz   17.57ns     3.99ns
diff --git a/saturn_alu.v b/saturn_alu.v
index 63dba75..aa43bcb 100644
--- a/saturn_alu.v
+++ b/saturn_alu.v
@@ -278,7 +278,8 @@ wire do_alu_pc;
 wire do_alu_mode;
 
 assign do_busclean = alu_active && i_en_alu_dump;
-assign do_alu_init = alu_active && i_en_alu_init && i_ins_alu_op && !alu_run && !write_done; 
+assign do_alu_init = alu_active && i_en_alu_init && i_ins_alu_op && !alu_run && 
+                     !write_done && !do_exec_p_eq; 
 assign do_alu_prep = alu_active && i_en_alu_prep && alu_run;
 assign do_alu_calc = alu_active && i_en_alu_calc && alu_run;
 assign do_alu_save = alu_active && i_en_alu_save && alu_run;
@@ -292,6 +293,24 @@ wire do_go_calc;
 assign do_go_init  = alu_active && i_en_alu_save && i_ins_test_go;
 assign do_go_prep  = alu_active && i_en_alu_prep && i_ins_test_go;
 
+// now for the fine tuning ;-)
+
+// save one cycle on P= n!
+wire   is_alu_op_copy;
+wire   is_reg_dest_p;
+wire   is_reg_src1_imm;
+wire   do_exec_p_eq;
+
+assign is_alu_op_copy  = (i_alu_op == `ALU_OP_COPY);
+assign is_reg_dest_p   = (i_reg_dest == `ALU_REG_P);
+assign is_reg_src1_imm = (i_reg_src1 == `ALU_REG_IMM);
+assign do_exec_p_eq    = alu_active && i_en_alu_save && i_ins_alu_op && is_alu_op_copy && is_reg_dest_p && is_reg_src1_imm;
+
+initial begin
+  // $monitor({"alu_active %b | i_en_alu_save %b | i_ins_alu_op %b | i_alu_op %0d | op=copy %b | i_reg_dest %0d | dest=P %b | i_reg_src1 %0d | src1=imm %b"},
+  //          alu_active, i_en_alu_save, i_ins_alu_op, i_alu_op, is_alu_op_copy, i_reg_dest, is_reg_dest_p, i_reg_src1, is_reg_src1_imm);
+end
+
 // the decoder may request the ALU to not stall it
 
 assign o_alu_stall_dec = (!no_extra_cycles) || 
@@ -671,6 +690,22 @@ always @(posedge i_clk) begin
     end
   end
 
+  /*
+   *
+   * Epic shortcut for P= n case
+   *
+   */
+
+  if (do_exec_p_eq) begin
+    P <= i_imm_value;
+  end
+
+  /*
+   * normal way for the ALU to save results. 
+   *
+   *
+   */
+
   if (do_alu_save) begin
     `ifdef SIM
     if (alu_debug) begin