implement more instructions, catch errors

This commit is contained in:
Raphael Jacquot 2019-02-07 23:31:35 +01:00
parent 55bdfed19a
commit 24c49893a1
7 changed files with 148 additions and 126 deletions

View file

@ -7,12 +7,16 @@
`define DEC_GOTO 2 // 6 `define DEC_GOTO 2 // 6
`define DEC_GOTO_LOOP 3 // 6[x] `define DEC_GOTO_LOOP 3 // 6[x]
`define DEC_GOTO_EXEC 4 // 6xxx -> exec `define DEC_GOTO_EXEC 4 // 6xxx -> exec
`define DEC_8 5 // 8X `define DEC_8X 5 // 8X
`define DEC_GOVLNG 6 // 8D `define DEC_80X 6 // 80X
`define DEC_GOVLNG_LOOP 7 // 8D[x] `define DEC_C_EQ_P_N 7 // 80Cm
`define DEC_GOVLNG_EXEC 8 // 8Dxxxxx -> exec `define DEC_ST_EQ_0_N 8 // 84n
`define DEC_GOSBVL 9 // 8F `define DEC_ST_EQ_1_N 9 // 85n
`define DEC_GOSBVL_LOOP 10 // 8F[x] `define DEC_GOVLNG 10 // 8D
`define DEC_GOSBVL_EXEC 11 // 8Fxxxxx -> exec `define DEC_GOVLNG_LOOP 11 // 8D[x]
`define DEC_GOVLNG_EXEC 12 // 8Dxxxxx -> exec
`define DEC_GOSBVL 13 // 8F
`define DEC_GOSBVL_LOOP 14 // 8F[x]
`define DEC_GOSBVL_EXEC 15 // 8Fxxxxx -> exec
`endif `endif

View file

@ -4,16 +4,12 @@
* *
*/ */
DECODE_C_EQ_P_N: `include "decstates.v"
begin
if (runstate == `RUN_DECODE) `DEC_C_EQ_P_N: begin
runstate <= `INSTR_START;
if (runstate == `INSTR_READY)
begin
C[nibble*4+:4] <= P; C[nibble*4+:4] <= P;
runstate <= `NEXT_INSTR; decstate <= `DEC_START;
`ifdef SIM `ifdef SIM
$display("%05h C=P\t%h", saved_PC, nibble); $display("%05h C=P\t%h", saved_PC, nibble);
`endif `endif
end end
end

View file

@ -5,31 +5,43 @@
* *
*/ */
DECODE_80: `include "decstates.v"
case (runstate)
`RUN_DECODE: runstate <= `INSTR_START; `DEC_80X: begin
`INSTR_START, `INSTR_STROBE: begin end
`INSTR_READY:
begin
case (nibble) case (nibble)
4'h5: decstate <= DECODE_CONFIG; 4'hc: decstate <= `DEC_C_EQ_P_N;
4'ha: decstate <= DECODE_RESET; default: begin
4'hc: decstate <= DECODE_C_EQ_P_N; $display("ERROR : DEC_80X");
default:
begin
`ifdef SIM
$display("unhandled instruction prefix 80%h", nibble);
`endif
decode_error <= 1;
end
endcase
runstate <= `RUN_DECODE;
end
default:
begin
`ifdef SIM
$display("DECODE_80: runstate %h", runstate);
`endif
decode_error <= 1; decode_error <= 1;
end end
endcase endcase
end
// DECODE_80:
// case (runstate)
// `RUN_DECODE: runstate <= `INSTR_START;
// `INSTR_START, `INSTR_STROBE: begin end
// `INSTR_READY:
// begin
// case (nibble)
// 4'h5: decstate <= DECODE_CONFIG;
// 4'ha: decstate <= DECODE_RESET;
// 4'hc: decstate <= DECODE_C_EQ_P_N;
// default:
// begin
// `ifdef SIM
// $display("unhandled instruction prefix 80%h", nibble);
// `endif
// decode_error <= 1;
// end
// endcase
// runstate <= `RUN_DECODE;
// end
// default:
// begin
// `ifdef SIM
// $display("DECODE_80: runstate %h", runstate);
// `endif
// decode_error <= 1;
// end
// endcase

View file

@ -3,28 +3,19 @@
* 85n ST=1 n * 85n ST=1 n
*/ */
DECODE_ST_EQ_0_N, DECODE_ST_EQ_1_N: `include "decstates.v"
begin
if (runstate == `RUN_DECODE) `DEC_ST_EQ_0_N: begin
runstate <= `INSTR_START;
if (runstate == `INSTR_READY)
begin
case (decstate)
DECODE_ST_EQ_0_N:
begin
ST[nibble] <= 0; ST[nibble] <= 0;
`ifdef SIM decstate <= `DEC_START;
`ifdef SIM
$display("%05h ST=0\t%h", saved_PC, nibble); $display("%05h ST=0\t%h", saved_PC, nibble);
`endif `endif
end end
DECODE_ST_EQ_1_N: `DEC_ST_EQ_1_N: begin
begin
ST[nibble] <= 1; ST[nibble] <= 1;
`ifdef SIM decstate <= `DEC_START;
`ifdef SIM
$display("%05h ST=1\t%h", saved_PC, nibble); $display("%05h ST=1\t%h", saved_PC, nibble);
`endif `endif
end end
endcase
runstate <= `NEXT_INSTR;
end
end

View file

@ -7,11 +7,17 @@
`include "decstates.v" `include "decstates.v"
`DEC_8: begin `DEC_8X: begin
case (nibble) case (nibble)
4'h0: decstate <= `DEC_80X;
4'h4: decstate <= `DEC_ST_EQ_0_N;
4'h5: decstate <= `DEC_ST_EQ_1_N;
4'hD: decstate <= `DEC_GOVLNG; 4'hD: decstate <= `DEC_GOVLNG;
4'hF: decstate <= `DEC_GOSBVL; 4'hF: decstate <= `DEC_GOSBVL;
default: begin end default: begin
$display("ERROR : DEC_8X");
decode_error <= 1;
end
endcase endcase
end end

View file

@ -14327,7 +14327,7 @@
} }
}, },
"cells": { "cells": {
"$abc$771$auto$blifparse.cc:492:parse_blif$772": { "$abc$2094$auto$blifparse.cc:492:parse_blif$2095": {
"hide_name": 1, "hide_name": 1,
"type": "LUT4", "type": "LUT4",
"parameters": { "parameters": {
@ -14352,7 +14352,7 @@
"Z": [ 22 ] "Z": [ 22 ]
} }
}, },
"$auto$alumacc.cc:474:replace_alu$625.slice[0].ccu2c_i": { "$auto$alumacc.cc:474:replace_alu$1931.slice[0].ccu2c_i": {
"hide_name": 1, "hide_name": 1,
"type": "CCU2C", "type": "CCU2C",
"parameters": { "parameters": {
@ -14363,7 +14363,7 @@
}, },
"attributes": { "attributes": {
"module_not_derived": 1, "module_not_derived": 1,
"src": "saturn_core.v:282|/usr/local/bin/../share/yosys/ecp5/arith_map.v:58" "src": "saturn_core.v:324|/usr/local/bin/../share/yosys/ecp5/arith_map.v:58"
}, },
"port_directions": { "port_directions": {
"A0": "input", "A0": "input",
@ -14394,7 +14394,7 @@
"S1": [ 25 ] "S1": [ 25 ]
} }
}, },
"$auto$alumacc.cc:474:replace_alu$625.slice[2].ccu2c_i": { "$auto$alumacc.cc:474:replace_alu$1931.slice[2].ccu2c_i": {
"hide_name": 1, "hide_name": 1,
"type": "CCU2C", "type": "CCU2C",
"parameters": { "parameters": {
@ -14405,7 +14405,7 @@
}, },
"attributes": { "attributes": {
"module_not_derived": 1, "module_not_derived": 1,
"src": "saturn_core.v:282|/usr/local/bin/../share/yosys/ecp5/arith_map.v:58" "src": "saturn_core.v:324|/usr/local/bin/../share/yosys/ecp5/arith_map.v:58"
}, },
"port_directions": { "port_directions": {
"A0": "input", "A0": "input",
@ -14436,7 +14436,7 @@
"S1": [ 28 ] "S1": [ 28 ]
} }
}, },
"$auto$simplemap.cc:420:simplemap_dff$696": { "$auto$simplemap.cc:420:simplemap_dff$2031": {
"hide_name": 1, "hide_name": 1,
"type": "TRELLIS_FF", "type": "TRELLIS_FF",
"parameters": { "parameters": {
@ -14449,7 +14449,7 @@
}, },
"attributes": { "attributes": {
"module_not_derived": 1, "module_not_derived": 1,
"src": "saturn_core.v:276|/usr/local/bin/../share/yosys/ecp5/cells_map.v:21" "src": "saturn_core.v:318|/usr/local/bin/../share/yosys/ecp5/cells_map.v:21"
}, },
"port_directions": { "port_directions": {
"CLK": "input", "CLK": "input",
@ -14464,7 +14464,7 @@
"Q": [ 10 ] "Q": [ 10 ]
} }
}, },
"$auto$simplemap.cc:420:simplemap_dff$697": { "$auto$simplemap.cc:420:simplemap_dff$2032": {
"hide_name": 1, "hide_name": 1,
"type": "TRELLIS_FF", "type": "TRELLIS_FF",
"parameters": { "parameters": {
@ -14477,7 +14477,7 @@
}, },
"attributes": { "attributes": {
"module_not_derived": 1, "module_not_derived": 1,
"src": "saturn_core.v:276|/usr/local/bin/../share/yosys/ecp5/cells_map.v:21" "src": "saturn_core.v:318|/usr/local/bin/../share/yosys/ecp5/cells_map.v:21"
}, },
"port_directions": { "port_directions": {
"CLK": "input", "CLK": "input",
@ -14492,7 +14492,7 @@
"Q": [ 11 ] "Q": [ 11 ]
} }
}, },
"$auto$simplemap.cc:420:simplemap_dff$698": { "$auto$simplemap.cc:420:simplemap_dff$2033": {
"hide_name": 1, "hide_name": 1,
"type": "TRELLIS_FF", "type": "TRELLIS_FF",
"parameters": { "parameters": {
@ -14505,7 +14505,7 @@
}, },
"attributes": { "attributes": {
"module_not_derived": 1, "module_not_derived": 1,
"src": "saturn_core.v:276|/usr/local/bin/../share/yosys/ecp5/cells_map.v:21" "src": "saturn_core.v:318|/usr/local/bin/../share/yosys/ecp5/cells_map.v:21"
}, },
"port_directions": { "port_directions": {
"CLK": "input", "CLK": "input",
@ -14520,7 +14520,7 @@
"Q": [ 12 ] "Q": [ 12 ]
} }
}, },
"$auto$simplemap.cc:420:simplemap_dff$699": { "$auto$simplemap.cc:420:simplemap_dff$2034": {
"hide_name": 1, "hide_name": 1,
"type": "TRELLIS_FF", "type": "TRELLIS_FF",
"parameters": { "parameters": {
@ -14533,7 +14533,7 @@
}, },
"attributes": { "attributes": {
"module_not_derived": 1, "module_not_derived": 1,
"src": "saturn_core.v:276|/usr/local/bin/../share/yosys/ecp5/cells_map.v:21" "src": "saturn_core.v:318|/usr/local/bin/../share/yosys/ecp5/cells_map.v:21"
}, },
"port_directions": { "port_directions": {
"CLK": "input", "CLK": "input",
@ -14548,7 +14548,7 @@
"Q": [ 13 ] "Q": [ 13 ]
} }
}, },
"$auto$simplemap.cc:420:simplemap_dff$700": { "$auto$simplemap.cc:420:simplemap_dff$2035": {
"hide_name": 1, "hide_name": 1,
"type": "TRELLIS_FF", "type": "TRELLIS_FF",
"parameters": { "parameters": {
@ -14561,7 +14561,7 @@
}, },
"attributes": { "attributes": {
"module_not_derived": 1, "module_not_derived": 1,
"src": "saturn_core.v:276|/usr/local/bin/../share/yosys/ecp5/cells_map.v:21" "src": "saturn_core.v:318|/usr/local/bin/../share/yosys/ecp5/cells_map.v:21"
}, },
"port_directions": { "port_directions": {
"CLK": "input", "CLK": "input",
@ -14576,7 +14576,7 @@
"Q": [ 14 ] "Q": [ 14 ]
} }
}, },
"$auto$simplemap.cc:420:simplemap_dff$701": { "$auto$simplemap.cc:420:simplemap_dff$2036": {
"hide_name": 1, "hide_name": 1,
"type": "TRELLIS_FF", "type": "TRELLIS_FF",
"parameters": { "parameters": {
@ -14589,7 +14589,7 @@
}, },
"attributes": { "attributes": {
"module_not_derived": 1, "module_not_derived": 1,
"src": "saturn_core.v:276|/usr/local/bin/../share/yosys/ecp5/cells_map.v:21" "src": "saturn_core.v:318|/usr/local/bin/../share/yosys/ecp5/cells_map.v:21"
}, },
"port_directions": { "port_directions": {
"CLK": "input", "CLK": "input",
@ -14604,7 +14604,7 @@
"Q": [ 15 ] "Q": [ 15 ]
} }
}, },
"$auto$simplemap.cc:420:simplemap_dff$702": { "$auto$simplemap.cc:420:simplemap_dff$2037": {
"hide_name": 1, "hide_name": 1,
"type": "TRELLIS_FF", "type": "TRELLIS_FF",
"parameters": { "parameters": {
@ -14617,7 +14617,7 @@
}, },
"attributes": { "attributes": {
"module_not_derived": 1, "module_not_derived": 1,
"src": "saturn_core.v:276|/usr/local/bin/../share/yosys/ecp5/cells_map.v:21" "src": "saturn_core.v:318|/usr/local/bin/../share/yosys/ecp5/cells_map.v:21"
}, },
"port_directions": { "port_directions": {
"CLK": "input", "CLK": "input",
@ -14632,7 +14632,7 @@
"Q": [ 16 ] "Q": [ 16 ]
} }
}, },
"$auto$simplemap.cc:420:simplemap_dff$703": { "$auto$simplemap.cc:420:simplemap_dff$2038": {
"hide_name": 1, "hide_name": 1,
"type": "TRELLIS_FF", "type": "TRELLIS_FF",
"parameters": { "parameters": {
@ -14645,7 +14645,7 @@
}, },
"attributes": { "attributes": {
"module_not_derived": 1, "module_not_derived": 1,
"src": "saturn_core.v:276|/usr/local/bin/../share/yosys/ecp5/cells_map.v:21" "src": "saturn_core.v:318|/usr/local/bin/../share/yosys/ecp5/cells_map.v:21"
}, },
"port_directions": { "port_directions": {
"CLK": "input", "CLK": "input",
@ -14660,7 +14660,7 @@
"Q": [ 17 ] "Q": [ 17 ]
} }
}, },
"$auto$simplemap.cc:420:simplemap_dff$704": { "$auto$simplemap.cc:420:simplemap_dff$2039": {
"hide_name": 1, "hide_name": 1,
"type": "TRELLIS_FF", "type": "TRELLIS_FF",
"parameters": { "parameters": {
@ -14673,7 +14673,7 @@
}, },
"attributes": { "attributes": {
"module_not_derived": 1, "module_not_derived": 1,
"src": "saturn_core.v:276|/usr/local/bin/../share/yosys/ecp5/cells_map.v:25" "src": "saturn_core.v:318|/usr/local/bin/../share/yosys/ecp5/cells_map.v:25"
}, },
"port_directions": { "port_directions": {
"CLK": "input", "CLK": "input",
@ -14688,7 +14688,7 @@
"Q": [ 18 ] "Q": [ 18 ]
} }
}, },
"$auto$simplemap.cc:420:simplemap_dff$705": { "$auto$simplemap.cc:420:simplemap_dff$2040": {
"hide_name": 1, "hide_name": 1,
"type": "TRELLIS_FF", "type": "TRELLIS_FF",
"parameters": { "parameters": {
@ -14701,7 +14701,7 @@
}, },
"attributes": { "attributes": {
"module_not_derived": 1, "module_not_derived": 1,
"src": "saturn_core.v:276|/usr/local/bin/../share/yosys/ecp5/cells_map.v:25" "src": "saturn_core.v:318|/usr/local/bin/../share/yosys/ecp5/cells_map.v:25"
}, },
"port_directions": { "port_directions": {
"CLK": "input", "CLK": "input",
@ -14716,7 +14716,7 @@
"Q": [ 19 ] "Q": [ 19 ]
} }
}, },
"$auto$simplemap.cc:420:simplemap_dff$706": { "$auto$simplemap.cc:420:simplemap_dff$2041": {
"hide_name": 1, "hide_name": 1,
"type": "TRELLIS_FF", "type": "TRELLIS_FF",
"parameters": { "parameters": {
@ -14729,7 +14729,7 @@
}, },
"attributes": { "attributes": {
"module_not_derived": 1, "module_not_derived": 1,
"src": "saturn_core.v:276|/usr/local/bin/../share/yosys/ecp5/cells_map.v:25" "src": "saturn_core.v:318|/usr/local/bin/../share/yosys/ecp5/cells_map.v:25"
}, },
"port_directions": { "port_directions": {
"CLK": "input", "CLK": "input",
@ -14744,7 +14744,7 @@
"Q": [ 20 ] "Q": [ 20 ]
} }
}, },
"$auto$simplemap.cc:420:simplemap_dff$707": { "$auto$simplemap.cc:420:simplemap_dff$2042": {
"hide_name": 1, "hide_name": 1,
"type": "TRELLIS_FF", "type": "TRELLIS_FF",
"parameters": { "parameters": {
@ -14757,7 +14757,7 @@
}, },
"attributes": { "attributes": {
"module_not_derived": 1, "module_not_derived": 1,
"src": "saturn_core.v:276|/usr/local/bin/../share/yosys/ecp5/cells_map.v:25" "src": "saturn_core.v:318|/usr/local/bin/../share/yosys/ecp5/cells_map.v:25"
}, },
"port_directions": { "port_directions": {
"CLK": "input", "CLK": "input",
@ -14774,30 +14774,31 @@
} }
}, },
"netnames": { "netnames": {
"$abc$771$n2": { "$abc$2094$n2": {
"hide_name": 1, "hide_name": 1,
"bits": [ 22 ], "bits": [ 22 ],
"attributes": { "attributes": {
} }
}, },
"$add$saturn_core.v:282$379_Y": { "$add$saturn_core.v:324$398_Y": {
"hide_name": 1, "hide_name": 1,
"bits": [ 24, 25, 27, 28 ], "bits": [ 24, 25, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56 ],
"attributes": { "attributes": {
"src": "saturn_core.v:324"
} }
}, },
"$auto$alumacc.cc:474:replace_alu$625.C": { "$auto$alumacc.cc:474:replace_alu$1931.C": {
"hide_name": 1, "hide_name": 1,
"bits": [ 29, 30, 23, 31 ], "bits": [ 57, 58, 23, 59 ],
"attributes": { "attributes": {
"src": "saturn_core.v:282|/usr/local/bin/../share/yosys/ecp5/arith_map.v:53" "src": "saturn_core.v:324|/usr/local/bin/../share/yosys/ecp5/arith_map.v:53"
} }
}, },
"$auto$alumacc.cc:474:replace_alu$625.FCO": { "$auto$alumacc.cc:474:replace_alu$1931.FCO": {
"hide_name": 1, "hide_name": 1,
"bits": [ 32, 33, 26, 34 ], "bits": [ 60, 61, 26, 62 ],
"attributes": { "attributes": {
"src": "saturn_core.v:282|/usr/local/bin/../share/yosys/ecp5/arith_map.v:54", "src": "saturn_core.v:324|/usr/local/bin/../share/yosys/ecp5/arith_map.v:54",
"unused_bits": "0 1 2 3" "unused_bits": "0 1 2 3"
} }
}, },
@ -14812,14 +14813,14 @@
"hide_name": 0, "hide_name": 0,
"bits": [ 4 ], "bits": [ 4 ],
"attributes": { "attributes": {
"src": "saturn_core.v:143|hp48_bus.v:38|hp48_io_ram.v:17" "src": "saturn_core.v:145|hp48_bus.v:38|hp48_io_ram.v:17"
} }
}, },
"bus_ctrl.reset": { "bus_ctrl.reset": {
"hide_name": 0, "hide_name": 0,
"bits": [ 4 ], "bits": [ 4 ],
"attributes": { "attributes": {
"src": "saturn_core.v:143|hp48_bus.v:19" "src": "saturn_core.v:145|hp48_bus.v:19"
} }
}, },
"clk": { "clk": {
@ -14847,7 +14848,7 @@
"hide_name": 0, "hide_name": 0,
"bits": [ 18, 19, 20, 21 ], "bits": [ 18, 19, 20, 21 ],
"attributes": { "attributes": {
"src": "saturn_core.v:90" "src": "saturn_core.v:92"
} }
}, },
"reset": { "reset": {

View file

@ -81,6 +81,7 @@ wire dec_strobe;
wire halt; wire halt;
reg [31:0] cycle_ctr; reg [31:0] cycle_ctr;
reg decode_error; reg decode_error;
reg debug_stop;
reg [3:0] busstate; reg [3:0] busstate;
reg read_next_pc; reg read_next_pc;
@ -168,6 +169,7 @@ initial
decstate = 0; decstate = 0;
$display("initializing control bits"); $display("initializing control bits");
decode_error = 0; decode_error = 0;
debug_stop = 0;
bus_load_pc = 1; bus_load_pc = 1;
read_next_pc = 1; read_next_pc = 1;
execute_cycle = 0; execute_cycle = 0;
@ -258,8 +260,8 @@ always @(posedge ph2)
end end
always @(posedge ph3) begin always @(posedge ph3) begin
if (cycle_ctr == 20) if (cycle_ctr == 48)
decode_error <= 1; debug_stop <= 1;
end end
//-------------------------------------------------------------------------------------------------- //--------------------------------------------------------------------------------------------------
@ -292,14 +294,24 @@ always @(posedge dec_strobe) begin
case (nibble) case (nibble)
4'h2: decstate <= `DEC_P_EQ_N; 4'h2: decstate <= `DEC_P_EQ_N;
4'h6: decstate <= `DEC_GOTO; 4'h6: decstate <= `DEC_GOTO;
4'h8: decstate <= `DEC_8; 4'h8: decstate <= `DEC_8X;
default: begin end default: begin
$display("ERROR : DEC_START");
decode_error <= 1;
end
endcase endcase
end end
`include "opcodes/2n_P_EQ_n.v" `include "opcodes/2n_P_EQ_n.v"
`include "opcodes/6xxx_GOTO.v" `include "opcodes/6xxx_GOTO.v"
`include "opcodes/8x.v" `include "opcodes/8x.v"
`include "opcodes/80x.v"
`include "opcodes/80Cn_C_EQ_P_n.v"
`include "opcodes/8[45]n_ST_EQ_[01]_n.v"
`include "opcodes/8[DF]xxxxx_GO.v" `include "opcodes/8[DF]xxxxx_GO.v"
default: begin
$display("ERROR : GENERAL");
decode_error <= 1;
end
endcase endcase
end end
@ -327,7 +339,7 @@ begin
end end
`endif `endif
assign halt = bus_error | decode_error; assign halt = bus_error | decode_error | debug_stop;
// Verilator lint_off UNUSED // Verilator lint_off UNUSED