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"saturn_core.v:222|/usr/local/bin/../share/yosys/ecp5/cells_map.v:8" }, "port_directions": { "CE": "input", @@ -33323,14 +34471,14 @@ "Q": "output" }, "connections": { - "CE": [ 807 ], - "CLK": [ 765 ], - "DI": [ 898 ], + "CE": [ 890 ], + "CLK": [ 833 ], + "DI": [ "1" ], "LSR": [ "0" ], "Q": [ 25 ] } }, - "$auto$simplemap.cc:420:simplemap_dff$8838": { + "$auto$simplemap.cc:420:simplemap_dff$9503": { "hide_name": 1, "type": "TRELLIS_FF", "parameters": { @@ -33342,7 +34490,7 @@ }, "attributes": { "module_not_derived": 1, - "src": "saturn_core.v:271|/usr/local/bin/../share/yosys/ecp5/cells_map.v:8" + "src": "saturn_core.v:222|/usr/local/bin/../share/yosys/ecp5/cells_map.v:8" }, "port_directions": { "CE": "input", @@ -33352,14 +34500,14 @@ "Q": "output" }, "connections": { - "CE": [ 807 ], - "CLK": [ 765 ], - "DI": [ 716 ], + "CE": [ 884 ], + "CLK": [ 833 ], + "DI": [ 151 ], "LSR": [ "0" ], - "Q": [ 34 ] + "Q": [ 20 ] } }, - "$auto$simplemap.cc:420:simplemap_dff$8839": { + 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"saturn_core.v:222|/usr/local/bin/../share/yosys/ecp5/cells_map.v:8" }, "port_directions": { "CE": "input", @@ -34599,14 +35515,14 @@ "Q": "output" }, "connections": { - "CE": [ 109 ], - "CLK": [ 765 ], - "DI": [ 919 ], + "CE": [ 885 ], + "CLK": [ 833 ], + "DI": [ 464 ], "LSR": [ "0" ], - "Q": [ 191 ] + "Q": [ 497 ] } }, - "$auto$simplemap.cc:420:simplemap_dff$8890": { + "$auto$simplemap.cc:420:simplemap_dff$9543": { "hide_name": 1, "type": "TRELLIS_FF", "parameters": { @@ -34618,7 +35534,7 @@ }, "attributes": { "module_not_derived": 1, - "src": "saturn_core.v:271|/usr/local/bin/../share/yosys/ecp5/cells_map.v:8" + "src": "saturn_core.v:222|/usr/local/bin/../share/yosys/ecp5/cells_map.v:8" }, "port_directions": { "CE": "input", @@ -34628,14 +35544,14 @@ "Q": "output" }, "connections": { - "CE": [ 149 ], - "CLK": [ 765 ], - "DI": [ 185 ], + "CE": [ 888 ], + "CLK": [ 833 ], + "DI": [ 467 ], "LSR": [ "0" ], - "Q": [ 73 ] + "Q": [ 474 ] } }, - "$auto$simplemap.cc:420:simplemap_dff$8891": { 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- "Q": "output" - }, - "connections": { - "CLK": [ 763 ], - "DI": [ 270 ], - "LSR": [ "0" ], - "Q": [ 276 ] - } - }, - "$auto$simplemap.cc:420:simplemap_dff$9000": { + "$auto$simplemap.cc:420:simplemap_dff$9552": { "hide_name": 1, "type": "TRELLIS_FF", "parameters": { @@ -36368,7 +35677,7 @@ }, "attributes": { "module_not_derived": 1, - "src": "saturn_core.v:141|hp48_bus.v:49|hp48_rom.v:48|/usr/local/bin/../share/yosys/ecp5/cells_map.v:8" + "src": "saturn_core.v:145|hp48_bus.v:49|hp48_rom.v:48|/usr/local/bin/../share/yosys/ecp5/cells_map.v:8" }, "port_directions": { "CE": "input", @@ -36378,14 +35687,14 @@ "Q": "output" }, "connections": { - "CE": [ 94 ], - "CLK": [ 763 ], - "DI": [ 768 ], + "CE": [ 21 ], + "CLK": [ 836 ], + "DI": [ 70 ], "LSR": [ "0" ], - "Q": [ 972 ] + "Q": [ 926 ] } }, - "$auto$simplemap.cc:420:simplemap_dff$9001": { + "$auto$simplemap.cc:420:simplemap_dff$9553": { "hide_name": 1, "type": "TRELLIS_FF", "parameters": { @@ -36397,7 +35706,7 @@ }, "attributes": { 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}, "connections": { - "CE": [ 94 ], - "CLK": [ 763 ], - "DI": [ 913 ], + "CE": [ 21 ], + "CLK": [ 836 ], + "DI": [ 64 ], "LSR": [ "0" ], - "Q": [ 983 ] + "Q": [ 937 ] } }, - "$auto$simplemap.cc:420:simplemap_dff$9003": { + "$auto$simplemap.cc:420:simplemap_dff$9555": { "hide_name": 1, "type": "TRELLIS_FF", "parameters": { @@ -36455,7 +35764,7 @@ }, "attributes": { "module_not_derived": 1, - "src": "saturn_core.v:141|hp48_bus.v:49|hp48_rom.v:48|/usr/local/bin/../share/yosys/ecp5/cells_map.v:8" + "src": "saturn_core.v:145|hp48_bus.v:49|hp48_rom.v:48|/usr/local/bin/../share/yosys/ecp5/cells_map.v:8" }, "port_directions": { "CE": "input", @@ -36465,14 +35774,14 @@ "Q": "output" }, "connections": { - "CE": [ 94 ], - "CLK": [ 763 ], - "DI": [ 916 ], + "CE": [ 21 ], + "CLK": [ 836 ], + "DI": [ 61 ], "LSR": [ "0" ], - "Q": [ 984 ] + "Q": [ 938 ] } }, - "$auto$simplemap.cc:420:simplemap_dff$9004": { + "$auto$simplemap.cc:420:simplemap_dff$9556": { "hide_name": 1, "type": "TRELLIS_FF", "parameters": { @@ -36484,7 +35793,7 @@ }, "attributes": { "module_not_derived": 1, - "src": "saturn_core.v:141|hp48_bus.v:49|hp48_rom.v:48|/usr/local/bin/../share/yosys/ecp5/cells_map.v:8" + "src": "saturn_core.v:145|hp48_bus.v:49|hp48_rom.v:48|/usr/local/bin/../share/yosys/ecp5/cells_map.v:8" }, "port_directions": { "CE": "input", @@ -36494,14 +35803,14 @@ "Q": "output" }, "connections": { - "CE": [ 94 ], - "CLK": [ 763 ], - "DI": [ 127 ], + "CE": [ 21 ], + "CLK": [ 836 ], + "DI": [ 58 ], "LSR": [ "0" ], - "Q": [ 986 ] + "Q": [ 940 ] } }, - "$auto$simplemap.cc:420:simplemap_dff$9005": { + "$auto$simplemap.cc:420:simplemap_dff$9557": { "hide_name": 1, "type": "TRELLIS_FF", "parameters": { @@ -36513,7 +35822,7 @@ }, "attributes": { "module_not_derived": 1, - "src": "saturn_core.v:141|hp48_bus.v:49|hp48_rom.v:48|/usr/local/bin/../share/yosys/ecp5/cells_map.v:8" + "src": "saturn_core.v:145|hp48_bus.v:49|hp48_rom.v:48|/usr/local/bin/../share/yosys/ecp5/cells_map.v:8" }, "port_directions": { "CE": "input", @@ -36523,14 +35832,14 @@ "Q": "output" }, "connections": { - "CE": [ 94 ], - "CLK": [ 763 ], - "DI": [ 130 ], + "CE": [ 21 ], + "CLK": [ 836 ], + "DI": [ 55 ], "LSR": [ "0" ], - "Q": [ 987 ] + "Q": [ 941 ] } }, - "$auto$simplemap.cc:420:simplemap_dff$9006": { + "$auto$simplemap.cc:420:simplemap_dff$9558": { "hide_name": 1, "type": "TRELLIS_FF", "parameters": { @@ -36542,7 +35851,7 @@ }, "attributes": { "module_not_derived": 1, - "src": "saturn_core.v:141|hp48_bus.v:49|hp48_rom.v:48|/usr/local/bin/../share/yosys/ecp5/cells_map.v:8" + "src": "saturn_core.v:145|hp48_bus.v:49|hp48_rom.v:48|/usr/local/bin/../share/yosys/ecp5/cells_map.v:8" }, "port_directions": { "CE": "input", @@ -36552,14 +35861,14 @@ "Q": "output" }, "connections": { - "CE": [ 94 ], - "CLK": [ 763 ], - "DI": [ 687 ], + "CE": [ 21 ], + "CLK": [ 836 ], + "DI": [ 52 ], "LSR": [ "0" ], - "Q": [ 989 ] + "Q": [ 943 ] } }, - "$auto$simplemap.cc:420:simplemap_dff$9007": { + "$auto$simplemap.cc:420:simplemap_dff$9559": { "hide_name": 1, "type": "TRELLIS_FF", "parameters": { @@ -36571,7 +35880,7 @@ }, "attributes": { "module_not_derived": 1, - "src": "saturn_core.v:141|hp48_bus.v:49|hp48_rom.v:48|/usr/local/bin/../share/yosys/ecp5/cells_map.v:8" + "src": "saturn_core.v:145|hp48_bus.v:49|hp48_rom.v:48|/usr/local/bin/../share/yosys/ecp5/cells_map.v:8" }, "port_directions": { "CE": "input", @@ -36581,14 +35890,14 @@ "Q": "output" }, "connections": { - "CE": [ 94 ], - "CLK": [ 763 ], - "DI": [ 906 ], + "CE": [ 21 ], + "CLK": [ 836 ], + "DI": [ 49 ], "LSR": [ "0" ], - "Q": [ 990 ] + "Q": [ 944 ] } }, - "$auto$simplemap.cc:420:simplemap_dff$9008": { + "$auto$simplemap.cc:420:simplemap_dff$9560": { "hide_name": 1, "type": "TRELLIS_FF", "parameters": { @@ -36600,7 +35909,7 @@ }, "attributes": { "module_not_derived": 1, - "src": "saturn_core.v:141|hp48_bus.v:49|hp48_rom.v:48|/usr/local/bin/../share/yosys/ecp5/cells_map.v:8" + "src": "saturn_core.v:145|hp48_bus.v:49|hp48_rom.v:48|/usr/local/bin/../share/yosys/ecp5/cells_map.v:8" }, "port_directions": { "CE": "input", @@ -36610,14 +35919,14 @@ "Q": "output" }, "connections": { - "CE": [ 94 ], - "CLK": [ 763 ], - "DI": [ 743 ], + "CE": [ 21 ], + "CLK": [ 836 ], + "DI": [ 46 ], "LSR": [ "0" ], - "Q": [ 992 ] + "Q": [ 946 ] } }, - "$auto$simplemap.cc:420:simplemap_dff$9009": { + "$auto$simplemap.cc:420:simplemap_dff$9561": { "hide_name": 1, "type": "TRELLIS_FF", "parameters": { @@ -36629,7 +35938,7 @@ }, "attributes": { "module_not_derived": 1, - "src": "saturn_core.v:141|hp48_bus.v:49|hp48_rom.v:48|/usr/local/bin/../share/yosys/ecp5/cells_map.v:8" + "src": "saturn_core.v:145|hp48_bus.v:49|hp48_rom.v:48|/usr/local/bin/../share/yosys/ecp5/cells_map.v:8" }, "port_directions": { "CE": "input", @@ -36639,14 +35948,14 @@ "Q": "output" }, "connections": { - "CE": [ 94 ], - "CLK": [ 763 ], - "DI": [ 384 ], + "CE": [ 21 ], + "CLK": [ 836 ], + "DI": [ 43 ], "LSR": [ "0" ], - "Q": [ 993 ] + "Q": [ 947 ] } }, - "$auto$simplemap.cc:420:simplemap_dff$9010": { + "$auto$simplemap.cc:420:simplemap_dff$9562": { "hide_name": 1, "type": "TRELLIS_FF", "parameters": { @@ -36658,7 +35967,7 @@ }, "attributes": { "module_not_derived": 1, - "src": "saturn_core.v:141|hp48_bus.v:49|hp48_rom.v:48|/usr/local/bin/../share/yosys/ecp5/cells_map.v:8" + "src": "saturn_core.v:145|hp48_bus.v:49|hp48_rom.v:48|/usr/local/bin/../share/yosys/ecp5/cells_map.v:8" }, "port_directions": { "CE": "input", @@ -36668,14 +35977,14 @@ "Q": "output" }, "connections": { - "CE": [ 94 ], - "CLK": [ 763 ], - "DI": [ 753 ], + "CE": [ 21 ], + "CLK": [ 836 ], + "DI": [ 40 ], "LSR": [ "0" ], - "Q": [ 975 ] + "Q": [ 929 ] } }, - "$auto$simplemap.cc:420:simplemap_dff$9011": { + "$auto$simplemap.cc:420:simplemap_dff$9563": { "hide_name": 1, "type": "TRELLIS_FF", "parameters": { @@ -36687,7 +35996,7 @@ }, "attributes": { "module_not_derived": 1, - "src": "saturn_core.v:141|hp48_bus.v:49|hp48_rom.v:48|/usr/local/bin/../share/yosys/ecp5/cells_map.v:8" + "src": "saturn_core.v:145|hp48_bus.v:49|hp48_rom.v:48|/usr/local/bin/../share/yosys/ecp5/cells_map.v:8" }, "port_directions": { "CE": "input", @@ -36697,14 +36006,14 @@ "Q": "output" }, "connections": { - "CE": [ 94 ], - "CLK": [ 763 ], - "DI": [ 746 ], + "CE": [ 21 ], + "CLK": [ 836 ], + "DI": [ 37 ], "LSR": [ "0" ], - "Q": [ 976 ] + "Q": [ 930 ] } }, - "$auto$simplemap.cc:420:simplemap_dff$9012": { + "$auto$simplemap.cc:420:simplemap_dff$9564": { "hide_name": 1, "type": "TRELLIS_FF", "parameters": { @@ -36716,7 +36025,7 @@ }, "attributes": { "module_not_derived": 1, - "src": "saturn_core.v:141|hp48_bus.v:49|hp48_rom.v:48|/usr/local/bin/../share/yosys/ecp5/cells_map.v:8" + "src": "saturn_core.v:145|hp48_bus.v:49|hp48_rom.v:48|/usr/local/bin/../share/yosys/ecp5/cells_map.v:8" }, "port_directions": { "CE": "input", @@ -36726,14 +36035,14 @@ "Q": "output" }, "connections": { - "CE": [ 94 ], - "CLK": [ 763 ], - "DI": [ 313 ], + "CE": [ 21 ], + "CLK": [ 836 ], + "DI": [ 34 ], "LSR": [ "0" ], - "Q": [ 979 ] + "Q": [ 933 ] } }, - "$auto$simplemap.cc:420:simplemap_dff$9013": { + "$auto$simplemap.cc:420:simplemap_dff$9565": { "hide_name": 1, "type": "TRELLIS_FF", "parameters": { @@ -36745,7 +36054,7 @@ }, "attributes": { "module_not_derived": 1, - "src": "saturn_core.v:141|hp48_bus.v:49|hp48_rom.v:48|/usr/local/bin/../share/yosys/ecp5/cells_map.v:8" + "src": "saturn_core.v:145|hp48_bus.v:49|hp48_rom.v:48|/usr/local/bin/../share/yosys/ecp5/cells_map.v:8" }, "port_directions": { "CE": "input", @@ -36755,14 +36064,14 @@ "Q": "output" }, "connections": { - "CE": [ 94 ], - "CLK": [ 763 ], - "DI": [ 681 ], + "CE": [ 21 ], + "CLK": [ 836 ], + "DI": [ 31 ], "LSR": [ "0" ], - "Q": [ 980 ] + "Q": [ 934 ] } }, - "$auto$simplemap.cc:420:simplemap_dff$9014": { + "$auto$simplemap.cc:420:simplemap_dff$9566": { "hide_name": 1, "type": "TRELLIS_FF", "parameters": { @@ -36774,7 +36083,7 @@ }, "attributes": { "module_not_derived": 1, - "src": "saturn_core.v:141|hp48_bus.v:49|hp48_rom.v:48|/usr/local/bin/../share/yosys/ecp5/cells_map.v:8" + "src": "saturn_core.v:145|hp48_bus.v:49|hp48_rom.v:48|/usr/local/bin/../share/yosys/ecp5/cells_map.v:8" }, "port_directions": { "CE": "input", @@ -36784,14 +36093,14 @@ "Q": "output" }, "connections": { - "CE": [ 94 ], - "CLK": [ 763 ], - "DI": [ 95 ], + "CE": [ 21 ], + "CLK": [ 836 ], + "DI": [ 28 ], "LSR": [ "0" ], - "Q": [ 266 ] + "Q": [ 231 ] } }, - "$auto$simplemap.cc:420:simplemap_dff$9015": { + "$auto$simplemap.cc:420:simplemap_dff$9567": { "hide_name": 1, "type": "TRELLIS_FF", "parameters": { @@ -36803,7 +36112,7 @@ }, "attributes": { "module_not_derived": 1, - "src": "saturn_core.v:141|hp48_bus.v:49|hp48_rom.v:48|/usr/local/bin/../share/yosys/ecp5/cells_map.v:8" + "src": "saturn_core.v:145|hp48_bus.v:49|hp48_rom.v:48|/usr/local/bin/../share/yosys/ecp5/cells_map.v:8" }, "port_directions": { "CE": "input", @@ -36813,11 +36122,11 @@ "Q": "output" }, "connections": { - "CE": [ 94 ], - "CLK": [ 763 ], - "DI": [ 771 ], + "CE": [ 21 ], + "CLK": [ 836 ], + "DI": [ 22 ], "LSR": [ "0" ], - "Q": [ 267 ] + "Q": [ 230 ] } }, "RSTK.0.0.0": { @@ -36841,12 +36150,12 @@ "WRE": "input" }, "connections": { - "DI": [ 785, 786, 787, 788 ], - "DO": [ 388, 406, 424, 442 ], - "RAD": [ 337, 348, 358, "0" ], - "WAD": [ 337, 348, 358, "0" ], - "WCK": [ 765 ], - "WRE": [ 759 ] + "DI": [ 839, 840, 841, 842 ], + "DO": [ 374, 795, 383, 802 ], + "RAD": [ 348, 355, 362, "0" ], + "WAD": [ 348, 355, 362, "0" ], + "WCK": [ 838 ], + "WRE": [ 832 ] } }, "RSTK.1.0.0": { @@ -36870,12 +36179,12 @@ "WRE": "input" }, "connections": { - "DI": [ 789, 790, 791, 792 ], - "DO": [ 460, 478, 497, 516 ], - "RAD": [ 337, 348, 358, "0" ], - "WAD": [ 337, 348, 358, "0" ], - "WCK": [ 765 ], - "WRE": [ 759 ] + "DI": [ 843, 844, 845, 846 ], + "DO": [ 392, 809, 400, 317 ], + "RAD": [ 348, 355, 362, "0" ], + "WAD": [ 348, 355, 362, "0" ], + "WCK": [ 838 ], + "WRE": [ 832 ] } }, "RSTK.2.0.0": { @@ -36899,12 +36208,12 @@ "WRE": "input" }, "connections": { - "DI": [ 794, 795, 796, 797 ], - "DO": [ 535, 553, 571, 590 ], - "RAD": [ 337, 348, 358, "0" ], - "WAD": [ 337, 348, 358, "0" ], - "WCK": [ 765 ], - "WRE": [ 759 ] + "DI": [ 847, 848, 849, 850 ], + "DO": [ 769, 325, 334, 484 ], + "RAD": [ 348, 355, 362, "0" ], + "WAD": [ 348, 355, 362, "0" ], + "WCK": [ 838 ], + "WRE": [ 832 ] } }, "RSTK.3.0.0": { @@ -36928,12 +36237,12 @@ "WRE": "input" }, "connections": { - "DI": [ 798, 799, 800, 801 ], - "DO": [ 608, 626, 644, 663 ], - "RAD": [ 337, 348, 358, "0" ], - "WAD": [ 337, 348, 358, "0" ], - "WCK": [ 765 ], - "WRE": [ 759 ] + "DI": [ 851, 852, 853, 854 ], + "DO": [ 483, 818, 823, 341 ], + "RAD": [ 348, 355, 362, "0" ], + "WAD": [ 348, 355, 362, "0" ], + "WCK": [ 838 ], + "WRE": [ 832 ] } }, "bus_ctrl.dev_rom.rom.0.0.0": { @@ -37090,24 +36399,24 @@ "ADA7": [ "0" ], "ADA8": [ "0" ], "ADA9": [ "0" ], - "ADB0": [ 972 ], - "ADB1": [ 973 ], - "ADB10": [ 975 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"attributes": { - "src": "saturn_core.v:141|hp48_bus.v:18" + "src": "saturn_core.v:145|hp48_bus.v:18" } }, "bus_ctrl_clk": { "hide_name": 0, - "bits": [ 760 ], + "bits": [ 833 ], "attributes": { "src": "saturn_core.v:65" } }, + "bus_load_pc": { + "hide_name": 0, + "bits": [ 149 ], + "attributes": { + "init": 1, + "src": "saturn_core.v:97" + } + }, "bus_nibble_out": { "hide_name": 0, - "bits": [ 275, 284, 291, 298 ], + "bits": [ 252, 261, 268, 275 ], "attributes": { - "src": "saturn_core.v:94" + "src": "saturn_core.v:95" } }, "bus_strobe": { "hide_name": 0, - "bits": [ 763 ], + "bits": [ 836 ], "attributes": { "src": "saturn_core.v:71" } @@ -45439,7 +43780,7 @@ }, "clk2": { "hide_name": 0, - "bits": [ 761 ], + "bits": [ 834 ], "attributes": { "init": 0, "src": "saturn_core.v:35" @@ -45447,7 +43788,7 @@ }, "clk3": { "hide_name": 0, - "bits": [ 373 ], + "bits": [ 235 ], "attributes": { "init": 0, "src": "saturn_core.v:64" @@ -45462,37 +43803,45 @@ }, "dec_strobe": { "hide_name": 0, - "bits": [ 765 ], + "bits": [ 838 ], "attributes": { "src": "saturn_core.v:73" } }, "decstate": { "hide_name": 0, - "bits": [ 21, 23, 25, 34, 26, 24, 31 ], + "bits": [ 82, 87, 77, 78, 90, 79, 80, 81 ], "attributes": { "init": 0, - "src": "saturn_core.v:87" + "src": "saturn_core.v:88" } }, "en_bus_clk": { "hide_name": 0, - "bits": [ 762 ], + "bits": [ 835 ], "attributes": { "init": 0, "src": "saturn_core.v:70" } }, + "en_bus_load_pc": { + "hide_name": 0, + "bits": [ 150 ], + "attributes": { + "init": 1, + "src": "saturn_core.v:98" + } + }, "en_dec_clk": { "hide_name": 0, - "bits": [ 764 ], + "bits": [ 837 ], "attributes": { "src": "saturn_core.v:72" } }, "execute_cycle": { "hide_name": 0, - "bits": [ 229 ], + "bits": [ 236 ], "attributes": { "init": 0, "src": "saturn_core.v:83" @@ -45500,24 +43849,32 @@ }, "hex_dec": { "hide_name": 0, - "bits": [ 994 ], + "bits": [ 736 ], "attributes": { "init": 0, - "src": "saturn_core.v:107" + "src": "saturn_core.v:111" + } + }, + "inc_pc": { + "hide_name": 0, + "bits": [ 742 ], + "attributes": { + "init": 0, + "src": "saturn_core.v:84" } }, "jump_base": { "hide_name": 0, - "bits": [ 386, 336, 105, 71, 305, 88, 495, 514, 533, 309, 326, 588, 317, 322, 330, 661, 1115, 1116, 1117, 1118 ], + "bits": [ 215, 172, 204, 418, 220, 182, 209, 224, 162, 178, 187, 192, 482, 476, 734, 197, 1055, 1056, 1057, 1058 ], "attributes": { - "src": "saturn_core.v:105" + "src": "saturn_core.v:109" } }, "jump_offset": { "hide_name": 0, - "bits": [ 257, 803, 375, 253, 920, 691, 708, 710, 712, 735, 737, 739, 747, 749, 754, 756, 1119, 1120, 1121, 1122 ], + "bits": [ 770, 296, 499, 693, 689, 691, 738, 740, 759, 761, 774, 780, 782, 784, 786, 788, 1059, 1060, 1061, 1062 ], "attributes": { - "src": "saturn_core.v:106" + "src": "saturn_core.v:110" } }, "led": { @@ -45527,25 +43884,41 @@ "src": "saturn_core.v:31" } }, + "new_PC": { + "hide_name": 0, + "bits": [ 373, 436, 382, 441, 391, 446, 399, 316, 453, 324, 333, 460, 463, 466, 469, 340, 1063, 1064, 1065, 1066 ], + "attributes": { + "init": 0, + "src": "saturn_core.v:105" + } + }, + "next_PC": { + "hide_name": 0, + "bits": [ 433, 435, 438, 440, 443, 445, 448, 450, 452, 455, 457, 459, 462, 465, 468, 471, 1067, 1068, 1069, 1070 ], + "attributes": { + "init": 0, + "src": "saturn_core.v:106" + } + }, "nibble": { "hide_name": 0, - "bits": [ 236, 89, 99, 65 ], + "bits": [ 163, 166, 188, 193 ], "attributes": { - "src": "saturn_core.v:102" + "src": "saturn_core.v:104" } }, "read_nibble": { "hide_name": 0, - "bits": [ 380 ], + "bits": [ 536 ], "attributes": { - "src": "saturn_core.v:84" + "src": "saturn_core.v:85" } }, "regdump": { "hide_name": 0, - "bits": [ 261, 262, 263, 264 ], + "bits": [ 225, 226, 227, 228 ], "attributes": { - "src": "saturn_core.v:88" + "src": "saturn_core.v:89" } }, "reset": { @@ -45557,24 +43930,24 @@ }, "rstk_ptr": { "hide_name": 0, - "bits": [ 337, 348, 358 ], + "bits": [ 348, 355, 362 ], "attributes": { "init": 7, - "src": "saturn_core.v:104" + "src": "saturn_core.v:108" } }, "t_cnt": { "hide_name": 0, - "bits": [ 188, 189, 190, 191 ], + "bits": [ 140, 142, 144, 146 ], "attributes": { - "src": "saturn_core.v:113" + "src": "saturn_core.v:117" } }, "t_ctr": { "hide_name": 0, - "bits": [ 73, 74, 75, 76 ], + "bits": [ 123, 141, 143, 145 ], "attributes": { - "src": "saturn_core.v:114" + "src": "saturn_core.v:118" } }, "wifi_gpio0": { diff --git a/saturn_core.v b/saturn_core.v index 0abc5c0..c9e65cb 100644 --- a/saturn_core.v +++ b/saturn_core.v @@ -95,6 +95,7 @@ reg [3:0] bus_nibble_in; wire [3:0] bus_nibble_out; wire bus_error; reg bus_load_pc; +reg en_bus_load_pc; // should go away, the rom should work like any other bus module reg rom_enable; @@ -102,6 +103,7 @@ reg rom_enable; // internal registers reg [3:0] nibble; reg [19:0] new_PC; +reg [19:0] next_PC; reg [19:0] inst_start_PC; reg [2:0] rstk_ptr; reg [19:0] jump_base; @@ -168,6 +170,7 @@ initial decode_error = 0; debug_stop = 0; bus_load_pc = 1; + en_bus_load_pc = 1; read_next_pc = 1; execute_cycle = 0; inc_pc = 0; @@ -175,6 +178,7 @@ initial hex_dec = `MODE_HEX; PC = 0; new_PC = 0; + next_PC = 0; inst_start_PC = 0; rstk_ptr = 7; @@ -182,6 +186,8 @@ initial // reset, clk, clk2, clk3, ph0, ph1, ph2, ph3, cycle_ctr, en_bus_clk, strobe, bus_load_pc, bus_nibble_in, bus_nibble_out, nibble); // $monitor("CTR %d | EBCLK %b| B_STRB %b | EDCLK %b | D_STRB %b | BLPC %b | bnbi %b | bnbo %b | nb %b ", // cycle_ctr, en_bus_clk, bus_strobe, en_dec_clk, dec_strobe, bus_load_pc, bus_nibble_in, bus_nibble_out, nibble); + // $monitor("BLPC %b | EBLPC %b", + // bus_load_pc, en_bus_load_pc); end //-------------------------------------------------------------------------------------------------- @@ -219,11 +225,13 @@ begin if (clk3) begin en_dec_clk <= 0; cycle_ctr <= cycle_ctr + 1; - if (bus_load_pc) begin + if (bus_load_pc&en_bus_load_pc) begin bus_command <= `BUSCMD_LOAD_PC; bus_address <= new_PC; - bus_load_pc <= 0; + next_PC <= new_PC; + PC <= new_PC; en_bus_clk <= 1; + en_bus_load_pc <= 0; //$display(">>>> PC load newPC %5h", new_PC); end else begin if (read_next_pc&~execute_cycle) begin @@ -231,8 +239,9 @@ begin bus_command <= `BUSCMD_PC_READ; read_nibble <= 1; en_bus_clk <= 1; - PC <= new_PC; + PC <= next_PC; inc_pc <= 1; + en_bus_load_pc <= 1; end else begin //$display(">>>> PC no change %5h", PC); $display("BUS NOT READING, STILL CLOCKING"); @@ -251,7 +260,7 @@ begin en_dec_clk <= 1; // PC does not change end if (inc_pc) begin - new_PC <= PC + 1; + next_PC <= PC + 1; inc_pc <= 0; //$display(">>>> PC inc to %5h", PC + 20'h1); end @@ -286,6 +295,7 @@ end `include "decstates.v" always @(posedge dec_strobe) begin + bus_load_pc <= 0; `ifdef SIM if (decstate == `DEC_START) begin // display registers