2019-02-08 23:59:56 +01:00
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/******************************************************************************
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* Dx
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* register manipulation field A
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*
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*/
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`include "decstates.v"
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`DEC_DX: begin
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2019-02-11 09:12:19 +01:00
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field <= `T_FIELD_A;
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alu_first <= 0;
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alu_last <= 4;
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case (nb_in[3:2])
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2'b00: begin
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alu_op <= `ALU_OP_ZERO;
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2019-02-11 11:29:31 +01:00
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alu_reg_dest <= reg_ABCD;
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2019-02-11 09:12:19 +01:00
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end
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2'b01: begin
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alu_op <= `ALU_OP_COPY;
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2019-02-11 11:29:31 +01:00
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alu_reg_dest <= reg_ABCD;
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alu_reg_src1 <= reg_BCAC;
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2019-02-08 23:59:56 +01:00
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end
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2019-02-11 09:12:19 +01:00
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2'b10: begin
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alu_op <= `ALU_OP_COPY;
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2019-02-11 11:29:31 +01:00
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alu_reg_dest <= reg_BCAC;
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alu_reg_src1 <= reg_ABCD;
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2019-02-08 23:59:56 +01:00
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end
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2019-02-11 09:12:19 +01:00
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2'b11: begin
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alu_op <= `ALU_OP_EXCH;
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2019-02-11 11:29:31 +01:00
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alu_reg_dest <= reg_ABAC;
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alu_reg_src1 <= reg_BCCD;
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2019-02-08 23:59:56 +01:00
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end
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endcase
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2019-02-11 09:12:19 +01:00
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next_cycle <= `BUSCMD_NOP;
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decstate <= `DEC_ALU_INIT;
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alu_return <= `DEC_START;
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2019-02-08 23:59:56 +01:00
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end
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