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fix fake pipeline: actually read words in arm pipeline, read correct regs
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commit
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1 changed files with 4 additions and 4 deletions
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@ -95,12 +95,12 @@ class CPU
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def fill_pipeline : Nil
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if @cpsr.thumb
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pc = @r[15] & ~1
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@pipeline.push @gba.bus.read_half(@r[15] &- 2).to_u32!
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@pipeline.push @gba.bus.read_half(@r[15]).to_u32!
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@pipeline.push @gba.bus.read_half(@r[15] &- 2).to_u32! if @pipeline.size == 0
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@pipeline.push @gba.bus.read_half(@r[15]).to_u32! if @pipeline.size == 1
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else
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pc = @r[15] & ~3
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@pipeline.push @gba.bus.read_half(@r[15] &- 4).to_u32!
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@pipeline.push @gba.bus.read_half(@r[15]).to_u32!
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@pipeline.push @gba.bus.read_word(@r[15] &- 4) if @pipeline.size == 0
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@pipeline.push @gba.bus.read_word(@r[15]) if @pipeline.size == 1
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end
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end
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