move cpsr onto new bitfield implementation

This commit is contained in:
Matthew Berry 2020-09-23 08:21:56 -07:00
parent e94754ca06
commit e9a1acb52a
6 changed files with 41 additions and 21 deletions

1
.gitignore vendored
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@ -3,3 +3,4 @@
/bin/
/.shards/
*.dwarf
/shard.lock

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@ -10,4 +10,9 @@ targets:
crystal: 0.35.1
dependencies:
bitfield:
github: mattrberry/bitfield
version: 0.1.0
license: MIT

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@ -1,3 +1,5 @@
require "bitfield"
require "./crab/gba"
module Crab

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@ -19,21 +19,21 @@ module ARM
private def check_cond(cond : Word) : Bool
case bits cond, 28..31
when 0x0 then bit?(@cpsr, 30) # Z
when 0x1 then !bit?(@cpsr, 30) # !Z
when 0x2 then bit?(@cpsr, 29) # C
when 0x3 then !bit?(@cpsr, 29) # !C
when 0x4 then bit?(@cpsr, 31) # N
when 0x5 then !bit?(@cpsr, 31) # !N
when 0x6 then bit?(@cpsr, 28) # V
when 0x7 then !bit?(@cpsr, 28) # !V
when 0x8 then bit?(@cpsr, 29) && !bit?(@cpsr, 30) # C && !Z
when 0x9 then !bit?(@cpsr, 29) || bit?(@cpsr, 30) # !C || Z
when 0xA then bit?(@cpsr, 31) == bit?(@cpsr, 28) # N == V
when 0xB then bit?(@cpsr, 31) != bit?(@cpsr, 28) # N != V
when 0xC then !bit?(@cpsr, 30) && bit?(@cpsr, 31) == bit?(@cpsr, 28) # !Z && N == V
when 0xD then bit?(@cpsr, 30) || bit?(@cpsr, 31) != bit?(@cpsr, 28) # Z || N != V
when 0xE then true # always
when 0x0 then @cpsr.zero
when 0x1 then !@cpsr.zero
when 0x2 then @cpsr.carry
when 0x3 then !@cpsr.carry
when 0x4 then @cpsr.negative
when 0x5 then !@cpsr.negative
when 0x6 then @cpsr.overflow
when 0x7 then !@cpsr.overflow
when 0x8 then @cpsr.carry && !@cpsr.zero
when 0x9 then !@cpsr.carry || @cpsr.zero
when 0xA then @cpsr.negative == @cpsr.overflow
when 0xB then @cpsr.negative != @cpsr.overflow
when 0xC then !@cpsr.zero && @cpsr.negative == @cpsr.overflow
when 0xD then @cpsr.zero || @cpsr.negative != @cpsr.overflow
when 0xE then true
else raise "Cond 0xF is reserved"
end
end

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@ -19,9 +19,9 @@ module ARM
when 0x2 then @r[rd] = rn &- operand_2
when 0x3 then @r[rd] = operand_2 &- rn
when 0x4 then @r[rd] = rn &+ operand_2
when 0x5 then @r[rd] = rn &+ operand_2 &+ (bit?(@cpsr, 29) ? 1 : 0)
when 0x6 then @r[rd] = rn &- operand_2 &+ (bit?(@cpsr, 29) ? 1 : 0) &- 1
when 0x7 then @r[rd] = operand_2 &- rn &+ (bit?(@cpsr, 29) ? 1 : 0) &- 1
when 0x5 then @r[rd] = rn &+ operand_2 &+ @cpsr.carry.to_unsafe
when 0x6 then @r[rd] = rn &- operand_2 &+ @cpsr.carry.to_unsafe &- 1
when 0x7 then @r[rd] = operand_2 &- rn &+ @cpsr.carry.to_unsafe &- 1
when 0x8
when 0x9
when 0xA

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@ -3,8 +3,20 @@ require "./arm/*"
class CPU
include ARM
class PSR < BitField(UInt32)
bool negative
bool zero
bool carry
bool overflow
num reserved, 20
bool irq_disable
bool fiq_disable
bool thumb
num mode, 5
end
@r = Slice(Word).new 16
@cpsr : UInt32 = 0
@cpsr : PSR
@pipeline = Deque(Word).new 2
getter lut : Slice(Proc(Word, Nil)) { fill_lut }
@ -13,7 +25,7 @@ class CPU
@r[1] = 0x000000EA
@r[13] = 0x03007F00
@r[15] = 0x08000000
@cpsr = 0x6000001F
@cpsr = PSR.new 0x6000001F
end
def fill_pipeline : Nil
@ -40,6 +52,6 @@ class CPU
@r.each do |reg|
trace "#{hex_str reg, prefix: false} ", newline: false
end
trace "cpsr: #{hex_str @cpsr, prefix: false} | #{hex_str instr, prefix: false}"
trace "cpsr: #{hex_str @cpsr.value, prefix: false} | #{hex_str instr, prefix: false}"
end
end