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fix stmia register order

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This commit is contained in:
Matthew Berry 2020-10-11 20:07:28 -07:00
parent 155f0a7f68
commit ad446281fc
2 changed files with 2 additions and 2 deletions
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2
src/crab/arm/block_data_transfer.cr
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@ -19,7 +19,7 @@ module ARM
end end
end end
else else
16.times do |idx| 15.downto(0).each do |idx|
if bit?(list, idx) if bit?(list, idx)
address &+= add ? 4 : -4 if pre_index address &+= add ? 4 : -4 if pre_index
@gba.bus[address] = @r[idx] @gba.bus[address] = @r[idx]

2
src/crab/thumb/multiple_load_store.cr
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@ -12,7 +12,7 @@ module THUMB
end end
end end
else # stmia else # stmia
8.times do |idx| 7.downto(0).each do |idx|
if bit?(list, idx) if bit?(list, idx)
@gba.bus[address] = @r[idx] @gba.bus[address] = @r[idx]
address &+= 4 address &+= 4