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add halting
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parent
042b76d910
commit
a79afb3817
3 changed files with 12 additions and 7 deletions
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@ -47,6 +47,7 @@ class CPU
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getter thumb_lut : Slice(Proc(Word, Nil)) { fill_thumb_lut }
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@reg_banks = Array(Array(Word)).new 6 { Array(Word).new 7, 0 }
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@spsr_banks = Array(Word).new 6, CPU::Mode::SYS.value # logically independent of typical register banks
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property halted = false
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def initialize(@gba : GBA)
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@reg_banks[Mode::USR.bank][5] = @r[13] = 0x03007F00
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@ -115,12 +116,14 @@ class CPU
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def tick : Nil
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fill_pipeline
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instr = @pipeline.shift
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{% if flag? :trace %} print_state instr {% end %}
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if @cpsr.thumb
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thumb_execute instr
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else
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arm_execute instr
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unless @halted
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instr = @pipeline.shift
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{% if flag? :trace %} print_state instr {% end %}
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if @cpsr.thumb
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thumb_execute instr
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else
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arm_execute instr
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end
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end
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@gba.tick 1
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end
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@ -55,7 +55,7 @@ class Interrupts
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private def check_interrupts : Nil
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if @reg_ie.value & @reg_if.value != 0
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# todo this condition unhalts
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@gba.cpu.halted = false
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@gba.cpu.irq if @ime
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end
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end
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@ -48,6 +48,8 @@ class MMIO
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shift = 8 * (io_addr & 1)
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mask = 0xFF00_u16 >> shift
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@waitcnt.value = (@waitcnt.value & mask) | value.to_u16 << shift
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elsif io_addr == 0x301
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@gba.cpu.halted = bit?(value, 7)
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elsif not_used? io_addr
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else
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puts "Unmapped MMIO write ~ addr:#{hex_str index.to_u32}, val:#{hex_str value}".colorize(:yellow)
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