arm branch exchange impl

src/crab/arm/arm.cr

@@ -62,7 +62,7 @@ module ARM
       elsif idx & 0b111001001001 == 0b000000001001
         # halfword data transfer register offset
       elsif idx & 0b111111111111 == 0b000100100001
-        # branch exchange
+        lut[idx] = ->arm_branch_exchange(Word)
       elsif idx & 0b111110111111 == 0b000100001001
         # single data swap
       elsif idx & 0b111110001111 == 0b000010001001

src/crab/arm/branch_exchange.cr

@@ -0,0 +1,12 @@
+module ARM
+  def arm_branch_exchange(instr : Word) : Nil
+    rn = bits(instr, 0..3)
+    if bit?(@r[rn], 0)
+      @cpsr.thumb = true
+      @r[15] = @r[rn] & ~1
+    else
+      @r[15] = @r[rn] & ~3
+    end
+    clear_pipeline
+  end
+end

src/crab/bus.cr

@@ -21,6 +21,11 @@ class Bus
       (self[index + 3].to_u32 << 24)
   end
 
+  def read_half(index : Int) : Word
+    self[index].to_u32 |
+      (self[index + 1].to_u32 << 8)
+  end
+
   def []=(index : Int, value : Byte) : Nil
     log "write #{hex_str index.to_u32} -> #{hex_str value}"
     case index

src/crab/cpu.cr

@@ -30,9 +30,15 @@ class CPU
 
   def fill_pipeline : Nil
     while @pipeline.size < 2
-      log "Fetch pc: #{hex_str @r[15]}, instr: #{hex_str @gba.bus.read_word @r[15]}"
-      @pipeline << @gba.bus.read_word @r[15]
-      @r[15] &+= 4
+      if @cpsr.thumb
+        log "Fetch pc: #{hex_str @r[15]}, instr: #{hex_str @gba.bus.read_half(@r[15]).to_u16}"
+        @pipeline << @gba.bus.read_half @r[15]
+        @r[15] &+= 2
+      else
+        log "Fetch pc: #{hex_str @r[15]}, instr: #{hex_str @gba.bus.read_word @r[15]}"
+        @pipeline << @gba.bus.read_word @r[15]
+        @r[15] &+= 4
+      end
     end
   end