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add (un)likely on obvious conditions
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parent
515d12aaa2
commit
8d9c789b94
3 changed files with 22 additions and 10 deletions
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@ -81,3 +81,15 @@ macro log(value, newline = true)
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{% end %}
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{% end %}
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{% end %}
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{% end %}
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end
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end
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lib LibIntrinsics
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fun expect_i1 = "llvm.expect.i1"(value : Bool, expected_value : Bool) : Bool
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end
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def likely(value : Bool)
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LibIntrinsics.expect_i1(value, true)
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end
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def unlikely(value : Bool)
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LibIntrinsics.expect_i1(value, false)
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end
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@ -161,8 +161,8 @@ module GBA
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@[AlwaysInline]
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@[AlwaysInline]
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private def write_byte_internal(index : Int, value : Byte) : Nil
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private def write_byte_internal(index : Int, value : Byte) : Nil
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return if bits(index, 28..31) > 0
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return if unlikely(bits(index, 28..31) > 0)
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@gba.cpu.fill_pipeline if index <= @gba.cpu.r[15] && index >= @gba.cpu.r[15] &- 4 # detect writes near pc
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@gba.cpu.fill_pipeline if unlikely(index <= @gba.cpu.r[15] && index >= @gba.cpu.r[15] &- 4) # detect writes near pc
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case bits(index, 24..27)
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case bits(index, 24..27)
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when 0x2 then @wram_board[index & 0x3FFFF] = value
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when 0x2 then @wram_board[index & 0x3FFFF] = value
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when 0x3 then @wram_chip[index & 0x7FFF] = value
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when 0x3 then @wram_chip[index & 0x7FFF] = value
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@ -181,9 +181,9 @@ module GBA
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@[AlwaysInline]
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@[AlwaysInline]
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private def write_half_internal(index : Int, value : HalfWord) : Nil
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private def write_half_internal(index : Int, value : HalfWord) : Nil
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return if bits(index, 28..31) > 0
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return if unlikely(bits(index, 28..31) > 0)
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index &= ~1
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index &= ~1
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@gba.cpu.fill_pipeline if index <= @gba.cpu.r[15] && index >= @gba.cpu.r[15] &- 4 # detect writes near pc
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@gba.cpu.fill_pipeline if unlikely(index <= @gba.cpu.r[15] && index >= @gba.cpu.r[15] &- 4) # detect writes near pc
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case bits(index, 24..27)
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case bits(index, 24..27)
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when 0x2 then (@wram_board.to_unsafe + (index & 0x3FFFF)).as(HalfWord*).value = value
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when 0x2 then (@wram_board.to_unsafe + (index & 0x3FFFF)).as(HalfWord*).value = value
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when 0x3 then (@wram_chip.to_unsafe + (index & 0x7FFF)).as(HalfWord*).value = value
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when 0x3 then (@wram_chip.to_unsafe + (index & 0x7FFF)).as(HalfWord*).value = value
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@ -202,9 +202,9 @@ module GBA
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@[AlwaysInline]
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@[AlwaysInline]
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private def write_word_internal(index : Int, value : Word) : Nil
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private def write_word_internal(index : Int, value : Word) : Nil
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return if bits(index, 28..31) > 0
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return if unlikely(bits(index, 28..31) > 0)
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index &= ~3
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index &= ~3
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@gba.cpu.fill_pipeline if index <= @gba.cpu.r[15] && index >= @gba.cpu.r[15] &- 4 # detect writes near pc
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@gba.cpu.fill_pipeline if unlikely(index <= @gba.cpu.r[15] && index >= @gba.cpu.r[15] &- 4) # detect writes near pc
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case bits(index, 24..27)
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case bits(index, 24..27)
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when 0x2 then (@wram_board.to_unsafe + (index & 0x3FFFF)).as(Word*).value = value
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when 0x2 then (@wram_board.to_unsafe + (index & 0x3FFFF)).as(Word*).value = value
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when 0x3 then (@wram_chip.to_unsafe + (index & 0x7FFF)).as(Word*).value = value
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when 0x3 then (@wram_chip.to_unsafe + (index & 0x7FFF)).as(Word*).value = value
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@ -119,7 +119,7 @@ module GBA
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end
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end
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def read_instr : Word
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def read_instr : Word
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if @pipeline.size == 0
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if likely(@pipeline.size == 0)
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if @cpsr.thumb
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if @cpsr.thumb
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@r[15] &= ~1
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@r[15] &= ~1
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@gba.bus.read_half(@r[15] &- 4).to_u32!
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@gba.bus.read_half(@r[15] &- 4).to_u32!
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@ -133,7 +133,7 @@ module GBA
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end
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end
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def tick : Nil
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def tick : Nil
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unless @halted
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unless unlikely(@halted)
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instr = read_instr
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instr = read_instr
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{% if flag? :trace %} print_state instr {% end %}
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{% if flag? :trace %} print_state instr {% end %}
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if @cpsr.thumb
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if @cpsr.thumb
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@ -150,6 +150,7 @@ module GBA
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def check_cond(cond : Word) : Bool
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def check_cond(cond : Word) : Bool
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case cond
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case cond
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when 0xE then true
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when 0x0 then @cpsr.zero
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when 0x0 then @cpsr.zero
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when 0x1 then !@cpsr.zero
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when 0x1 then !@cpsr.zero
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when 0x2 then @cpsr.carry
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when 0x2 then @cpsr.carry
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@ -164,7 +165,6 @@ module GBA
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when 0xB then @cpsr.negative != @cpsr.overflow
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when 0xB then @cpsr.negative != @cpsr.overflow
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when 0xC then !@cpsr.zero && @cpsr.negative == @cpsr.overflow
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when 0xC then !@cpsr.zero && @cpsr.negative == @cpsr.overflow
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when 0xD then @cpsr.zero || @cpsr.negative != @cpsr.overflow
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when 0xD then @cpsr.zero || @cpsr.negative != @cpsr.overflow
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when 0xE then true
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else raise "Cond 0xF is reserved"
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else raise "Cond 0xF is reserved"
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end
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end
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end
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end
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@ -180,7 +180,7 @@ module GBA
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@[AlwaysInline]
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@[AlwaysInline]
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def set_reg(reg : Int, value : Int) : UInt32
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def set_reg(reg : Int, value : Int) : UInt32
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@r[reg] = value.to_u32!
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@r[reg] = value.to_u32!
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clear_pipeline if reg == 15
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clear_pipeline if unlikely(reg == 15)
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value.to_u32!
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value.to_u32!
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end
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end
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