diff --git a/src/crab/gba/arm/arm.cr b/src/crab/gba/arm/arm.cr
index 9c9010e..f263d79 100644
--- a/src/crab/gba/arm/arm.cr
+++ b/src/crab/gba/arm/arm.cr
@@ -47,9 +47,9 @@ module GBA
         elsif idx & 0b111111001111 == 0b000000001001
           lut[idx] = ->arm_multiply(UInt32)
         elsif idx & 0b111001001001 == 0b000001001001
-          lut[idx] = ->arm_UInt16_data_transfer_immediate(UInt32)
+          lut[idx] = ->arm_halfword_data_transfer_immediate(UInt32)
         elsif idx & 0b111001001001 == 0b000000001001
-          lut[idx] = ->arm_UInt16_data_transfer_register(UInt32)
+          lut[idx] = ->arm_halfword_data_transfer_register(UInt32)
         elsif idx & 0b110110010000 == 0b000100000000
           lut[idx] = ->arm_psr_transfer(UInt32)
         elsif idx & 0b110000000000 == 0b000000000000
diff --git a/src/crab/gba/arm/halfword_data_transfer_imm.cr b/src/crab/gba/arm/halfword_data_transfer_imm.cr
index 0891d97..7e1e94e 100644
--- a/src/crab/gba/arm/halfword_data_transfer_imm.cr
+++ b/src/crab/gba/arm/halfword_data_transfer_imm.cr
@@ -1,6 +1,6 @@
 module GBA
   module ARM
-    def arm_UInt16_data_transfer_immediate(instr : UInt32) : Nil
+    def arm_halfword_data_transfer_immediate(instr : UInt32) : Nil
       pre_address = bit?(instr, 24)
       add = bit?(instr, 23)
       write_back = bit?(instr, 21)
@@ -24,7 +24,7 @@ module GBA
 
       case sh
       when 0b00 # swp, no docs on this?
-        abort "UInt16DataTransferReg swp #{hex_str instr}"
+        abort "HalfwordDataTransferReg swp #{hex_str instr}"
       when 0b01 # ldrh/strh
         if load
           set_reg(rd, @gba.bus.read_half_rotate address)
diff --git a/src/crab/gba/arm/halfword_data_transfer_reg.cr b/src/crab/gba/arm/halfword_data_transfer_reg.cr
index a6eb442..189ff89 100644
--- a/src/crab/gba/arm/halfword_data_transfer_reg.cr
+++ b/src/crab/gba/arm/halfword_data_transfer_reg.cr
@@ -1,6 +1,6 @@
 module GBA
   module ARM
-    def arm_UInt16_data_transfer_register(instr : UInt32) : Nil
+    def arm_halfword_data_transfer_register(instr : UInt32) : Nil
       pre_address = bit?(instr, 24)
       add = bit?(instr, 23)
       write_back = bit?(instr, 21)
@@ -23,7 +23,7 @@ module GBA
 
       case sh
       when 0b00 # swp, no docs on this?
-        abort "UInt16DataTransferReg swp #{hex_str instr}"
+        abort "HalfwordDataTransferReg swp #{hex_str instr}"
       when 0b01 # ldrh/strh
         if load
           set_reg(rd, @gba.bus.read_half_rotate address)
diff --git a/src/crab/gba/thumb/load_store_halfword.cr b/src/crab/gba/thumb/load_store_halfword.cr
index 7169c29..e95d45f 100644
--- a/src/crab/gba/thumb/load_store_halfword.cr
+++ b/src/crab/gba/thumb/load_store_halfword.cr
@@ -1,6 +1,6 @@
 module GBA
   module THUMB
-    def thumb_load_store_UInt16(instr : UInt32) : Nil
+    def thumb_load_store_halfword(instr : UInt32) : Nil
       load = bit?(instr, 11)
       offset = bits(instr, 6..10)
       rb = bits(instr, 3..5)
diff --git a/src/crab/gba/thumb/thumb.cr b/src/crab/gba/thumb/thumb.cr
index 9bbe839..603cc25 100644
--- a/src/crab/gba/thumb/thumb.cr
+++ b/src/crab/gba/thumb/thumb.cr
@@ -26,7 +26,7 @@ module GBA
         elsif idx & 0b11110000 == 0b10010000
           lut[idx] = ->thumb_sp_relative_load_store(UInt32)
         elsif idx & 0b11110000 == 0b10000000
-          lut[idx] = ->thumb_load_store_UInt16(UInt32)
+          lut[idx] = ->thumb_load_store_halfword(UInt32)
         elsif idx & 0b11100000 == 0b01100000
           lut[idx] = ->thumb_load_store_immediate_offset(UInt32)
         elsif idx & 0b11110010 == 0b01010010