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fix timing of thumb ldmia writeback

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This commit is contained in:
Matthew Berry 2021-06-06 12:46:50 -07:00
parent e706c5f64f
commit 3b71156bd3
1 changed files with 5 additions and 2 deletions
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7
src/crab/gba/thumb/multiple_load_store.cr
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@ -6,7 +6,9 @@ module GBA
list = bits(instr, 0..7)
address = @r[rb]
unless list == 0
final_addr = 4_u32 * list.popcount + address
if load # ldmia
@r[rb] = final_addr # thumb ldmia writes back immediately
8.times do |idx|
if bit?(list, idx)
set_reg(idx, @gba.bus.read_word(address))
@ -15,16 +17,17 @@ module GBA
end
else # stmia
base_addr = nil
first_transfer = false
8.times do |idx|
if bit?(list, idx)
@gba.bus[address] = @r[idx]
base_addr = address if rb == idx
address &+= 4
@r[rb] = final_addr unless first_transfer # thumb stdmia writes back after first transfer
first_transfer = true
end
end
@gba.bus[base_addr] = address if base_addr && first_set_bit(list) != rb # rb is written after first store
end
set_reg(rb, address)
else # https://github.com/jsmolka/gba-suite/blob/0e32e15c6241e6dc20851563ba88f4656ac50936/thumb/memory.asm#L459
if load
set_reg(15, @gba.bus.read_word(address))