clear pipeline if rd==15 in thumb hi-reg bx, load/store imm, load/store reg

This commit is contained in:
Matthew Berry 2020-10-11 10:29:22 -07:00
parent b52599ae2d
commit 367b578d9f
3 changed files with 26 additions and 17 deletions

View file

@ -22,5 +22,6 @@ module THUMB
end end
clear_pipeline clear_pipeline
end end
clear_pipeline if rd == 15
end end
end end

View file

@ -5,11 +5,16 @@ module THUMB
rb = bits(instr, 3..5) rb = bits(instr, 3..5)
rd = bits(instr, 0..2) rd = bits(instr, 0..2)
imm = offset << 2 imm = offset << 2
address = @r[rb] &+ (offset << 2)
case byte_quantity_and_load case byte_quantity_and_load
when 0b00 then @gba.bus[@r[rb] + imm] = @r[rd] when 0b00 then @gba.bus[address] = @r[rd]
when 0b01 then @r[rd] = @gba.bus.read_word(@r[rb] + imm) when 0b01
when 0b10 then @gba.bus[@r[rb] + imm] = @r[rd].to_u8! @r[rd] = @gba.bus.read_word(address)
when 0b11 then @r[rd] = @gba.bus[@r[rb] + imm].to_u32 clear_pipeline if rd == 15
when 0b10 then @gba.bus[address] = 0xFF_u8 & @r[rd]
when 0b11
@r[rd] = 0xFFFFFFFF_u32 & @gba.bus[address]
clear_pipeline if rd == 15
end end
end end
end end

View file

@ -8,9 +8,12 @@ module THUMB
case load_and_byte_quantity case load_and_byte_quantity
when 0b00 then @gba.bus[address] = @r[rd] when 0b00 then @gba.bus[address] = @r[rd]
when 0b01 then @gba.bus[address] = 0xFF_u8 & @r[rd] when 0b01 then @gba.bus[address] = 0xFF_u8 & @r[rd]
when 0b10 then @r[rd] = @gba.bus.read_word address when 0b10
when 0b11 then @r[rd] = 0xFFFFFFFF_u32 & @gba.bus[address] @r[rd] = @gba.bus.read_word address
clear_pipeline if rd == 15
when 0b11
@r[rd] = 0xFFFFFFFF_u32 & @gba.bus[address]
clear_pipeline if rd == 15
end end
end end
end end