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clear pipeline if rd==15 in thumb hi-reg bx, load/store imm, load/store reg
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parent
b52599ae2d
commit
367b578d9f
3 changed files with 26 additions and 17 deletions
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@ -22,5 +22,6 @@ module THUMB
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end
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end
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clear_pipeline
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clear_pipeline
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end
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end
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clear_pipeline if rd == 15
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end
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end
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end
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end
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@ -5,11 +5,16 @@ module THUMB
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rb = bits(instr, 3..5)
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rb = bits(instr, 3..5)
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rd = bits(instr, 0..2)
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rd = bits(instr, 0..2)
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imm = offset << 2
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imm = offset << 2
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address = @r[rb] &+ (offset << 2)
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case byte_quantity_and_load
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case byte_quantity_and_load
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when 0b00 then @gba.bus[@r[rb] + imm] = @r[rd]
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when 0b00 then @gba.bus[address] = @r[rd]
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when 0b01 then @r[rd] = @gba.bus.read_word(@r[rb] + imm)
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when 0b01
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when 0b10 then @gba.bus[@r[rb] + imm] = @r[rd].to_u8!
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@r[rd] = @gba.bus.read_word(address)
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when 0b11 then @r[rd] = @gba.bus[@r[rb] + imm].to_u32
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clear_pipeline if rd == 15
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when 0b10 then @gba.bus[address] = 0xFF_u8 & @r[rd]
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when 0b11
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@r[rd] = 0xFFFFFFFF_u32 & @gba.bus[address]
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clear_pipeline if rd == 15
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end
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end
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end
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end
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end
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end
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@ -8,9 +8,12 @@ module THUMB
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case load_and_byte_quantity
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case load_and_byte_quantity
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when 0b00 then @gba.bus[address] = @r[rd]
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when 0b00 then @gba.bus[address] = @r[rd]
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when 0b01 then @gba.bus[address] = 0xFF_u8 & @r[rd]
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when 0b01 then @gba.bus[address] = 0xFF_u8 & @r[rd]
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when 0b10 then @r[rd] = @gba.bus.read_word address
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when 0b10
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when 0b11 then @r[rd] = 0xFFFFFFFF_u32 & @gba.bus[address]
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@r[rd] = @gba.bus.read_word address
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clear_pipeline if rd == 15
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when 0b11
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@r[rd] = 0xFFFFFFFF_u32 & @gba.bus[address]
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clear_pipeline if rd == 15
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end
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end
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end
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end
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end
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end
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