mirror of
https://github.com/SlackBuildsOrg/slackbuilds
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| README | ||
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| verilog.info | ||
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Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the 'vvp' command. For synthesis, the compiler generates netlists in the desired format.