diff --git a/ChocolArm64/AOpCodeTable.cs b/ChocolArm64/AOpCodeTable.cs
index 13df4d9868..e192f5ec5e 100644
--- a/ChocolArm64/AOpCodeTable.cs
+++ b/ChocolArm64/AOpCodeTable.cs
@@ -230,7 +230,7 @@ namespace ChocolArm64
             Set("0x10111000100000010110xxxxxxxxxx", AInstEmit.Not_V,         typeof(AOpCodeSimd));
             Set("0x001110101xxxxx000111xxxxxxxxxx", AInstEmit.Orr_V,         typeof(AOpCodeSimdReg));
             Set("0x00111100000xxx<<x101xxxxxxxxxx", AInstEmit.Orr_Vi,        typeof(AOpCodeSimdImm));
-            Set("0x001110xx100000000010xxxxxxxxxx", AInstEmit.Rev64_V,       typeof(AOpCodeSimd));
+            Set("0x001110<<100000000010xxxxxxxxxx", AInstEmit.Rev64_V,       typeof(AOpCodeSimd));
             Set("0x001110<<1xxxxx000100xxxxxxxxxx", AInstEmit.Saddw_V,       typeof(AOpCodeSimdReg));
             Set("x0011110xx100010000000xxxxxxxxxx", AInstEmit.Scvtf_Gp,      typeof(AOpCodeSimdCvt));
             Set("010111100x100001110110xxxxxxxxxx", AInstEmit.Scvtf_S,       typeof(AOpCodeSimd));
diff --git a/ChocolArm64/Instruction/AInstEmitSimdLogical.cs b/ChocolArm64/Instruction/AInstEmitSimdLogical.cs
index f4cc66cf68..5b71a0bbb8 100644
--- a/ChocolArm64/Instruction/AInstEmitSimdLogical.cs
+++ b/ChocolArm64/Instruction/AInstEmitSimdLogical.cs
@@ -1,5 +1,6 @@
+using ChocolArm64.Decoder;
+using ChocolArm64.State;
 using ChocolArm64.Translation;
-using System;
 using System.Reflection.Emit;
 
 using static ChocolArm64.Instruction.AInstEmitSimdHelper;
@@ -69,12 +70,25 @@ namespace ChocolArm64.Instruction
 
         public static void Rev64_V(AILEmitterCtx Context)
         {
-            Action Emit = () =>
+            AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
+
+            int Bytes = Context.CurrOp.GetBitsCount() >> 3;
+
+            int Elems = Bytes >> Op.Size;
+
+            int RevIndex = Elems - 1;
+
+            for (int Index = 0; Index < (Bytes >> Op.Size); Index++)
             {
-                ASoftFallback.EmitCall(Context, nameof(ASoftFallback.ReverseBits64));
-            };
-            
-            EmitVectorUnaryOpZx(Context, Emit);
+                EmitVectorExtractZx(Context, Op.Rn, RevIndex--, Op.Size);
+
+                EmitVectorInsert(Context, Op.Rd, Index, Op.Size);
+            }
+
+            if (Op.RegisterSize == ARegisterSize.SIMD64)
+            {
+                EmitVectorZeroUpper(Context, Op.Rd);
+            }
         }
     }
 }
\ No newline at end of file
diff --git a/ChocolArm64/Instruction/ASoftFallback.cs b/ChocolArm64/Instruction/ASoftFallback.cs
index 5127182ddc..797d815736 100644
--- a/ChocolArm64/Instruction/ASoftFallback.cs
+++ b/ChocolArm64/Instruction/ASoftFallback.cs
@@ -75,7 +75,7 @@ namespace ChocolArm64.Instruction
 
         private static ulong ReverseBytes(ulong Value, RevSize Size)
         {
-            Value = ((Value & 0xff00ff00ff00ff00) >>  8) | ((Value & 0x00ff00ff00ff00ff) <<  8);
+            Value = ((Value & 0xff00ff00ff00ff00) >> 8) | ((Value & 0x00ff00ff00ff00ff) << 8);
 
             if (Size == RevSize.Rev16)
             {