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Add MLS (vector) instruction, fix mistake introduced on last commit

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This commit is contained in:
gdkchan 2018-02-18 02:13:42 -03:00
parent c3b5b4ffeb
commit 3872ae034d
3 changed files with 19 additions and 5 deletions
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1
Ryujinx/Cpu/AOpCodeTable.cs
View file

@ -203,6 +203,7 @@ namespace ChocolArm64
Set("xx111100x11xxxxxxxxx10xxxxxxxxxx", AInstEmit.Ldr, typeof(AOpCodeSimdMemReg)); Set("xx111100x11xxxxxxxxx10xxxxxxxxxx", AInstEmit.Ldr, typeof(AOpCodeSimdMemReg));
Set("xx011100xxxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.LdrLit, typeof(AOpCodeSimdMemLit)); Set("xx011100xxxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.LdrLit, typeof(AOpCodeSimdMemLit));
Set("0x001110<<1xxxxx100101xxxxxxxxxx", AInstEmit.Mla_V, typeof(AOpCodeSimdReg)); Set("0x001110<<1xxxxx100101xxxxxxxxxx", AInstEmit.Mla_V, typeof(AOpCodeSimdReg));
Set("0x101110<<1xxxxx100101xxxxxxxxxx", AInstEmit.Mls_V, typeof(AOpCodeSimdReg));
Set("0x00111100000xxx0xx001xxxxxxxxxx", AInstEmit.Movi_V, typeof(AOpCodeSimdImm)); Set("0x00111100000xxx0xx001xxxxxxxxxx", AInstEmit.Movi_V, typeof(AOpCodeSimdImm));
Set("0x00111100000xxx10x001xxxxxxxxxx", AInstEmit.Movi_V, typeof(AOpCodeSimdImm)); Set("0x00111100000xxx10x001xxxxxxxxxx", AInstEmit.Movi_V, typeof(AOpCodeSimdImm));
Set("0x00111100000xxx110x01xxxxxxxxxx", AInstEmit.Movi_V, typeof(AOpCodeSimdImm)); Set("0x00111100000xxx110x01xxxxxxxxxx", AInstEmit.Movi_V, typeof(AOpCodeSimdImm));

12
Ryujinx/Cpu/Instruction/AInstEmitSimdArithmetic.cs
View file

@ -182,8 +182,7 @@ namespace ChocolArm64.Instruction
EmitScalarTernaryRaOpF(Context, () => EmitScalarTernaryRaOpF(Context, () =>
{ {
Context.Emit(OpCodes.Mul); Context.Emit(OpCodes.Mul);
Context.Emit(OpCodes.Neg); Context.Emit(OpCodes.Sub);
Context.Emit(OpCodes.Add);
}); });
} }
@ -262,6 +261,15 @@ namespace ChocolArm64.Instruction
}); });
} }
public static void Mls_V(AILEmitterCtx Context)
{
EmitVectorTernaryOpZx(Context, () =>
{
Context.Emit(OpCodes.Mul);
Context.Emit(OpCodes.Sub);
});
}
public static void Mul_V(AILEmitterCtx Context) public static void Mul_V(AILEmitterCtx Context)
{ {
EmitVectorBinaryOpZx(Context, () => Context.Emit(OpCodes.Mul)); EmitVectorBinaryOpZx(Context, () => Context.Emit(OpCodes.Mul));

11
Ryujinx/Cpu/Instruction/AInstEmitSimdHelper.cs
View file

@ -210,14 +210,14 @@ namespace ChocolArm64.Instruction
{ {
AOpCodeSimdRegElem Op = (AOpCodeSimdRegElem)Context.CurrOp; AOpCodeSimdRegElem Op = (AOpCodeSimdRegElem)Context.CurrOp;
EmitVectorOpByElemF(Context, Emit, Op.Index); EmitVectorOpByElemF(Context, Emit, Op.Index, Ternary: false);
} }
public static void EmitVectorTernaryOpByElemF(AILEmitterCtx Context, Action Emit) public static void EmitVectorTernaryOpByElemF(AILEmitterCtx Context, Action Emit)
{ {
AOpCodeSimdRegElem Op = (AOpCodeSimdRegElem)Context.CurrOp; AOpCodeSimdRegElem Op = (AOpCodeSimdRegElem)Context.CurrOp;
EmitVectorOpByElemF(Context, Emit, Op.Index); EmitVectorOpByElemF(Context, Emit, Op.Index, Ternary: true);
} }
public static void EmitVectorOpF(AILEmitterCtx Context, Action Emit, OperFlags Opers) public static void EmitVectorOpF(AILEmitterCtx Context, Action Emit, OperFlags Opers)
@ -256,7 +256,7 @@ namespace ChocolArm64.Instruction
} }
} }
public static void EmitVectorOpByElemF(AILEmitterCtx Context, Action Emit, int Elem) public static void EmitVectorOpByElemF(AILEmitterCtx Context, Action Emit, int Elem, bool Ternary)
{ {
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp; AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
@ -266,6 +266,11 @@ namespace ChocolArm64.Instruction
for (int Index = 0; Index < (Bytes >> SizeF + 2); Index++) for (int Index = 0; Index < (Bytes >> SizeF + 2); Index++)
{ {
if (Ternary)
{
EmitVectorExtractF(Context, Op.Rd, Index, SizeF);
}
EmitVectorExtractF(Context, Op.Rn, Index, SizeF); EmitVectorExtractF(Context, Op.Rn, Index, SizeF);
EmitVectorExtractF(Context, Op.Rm, Elem, SizeF); EmitVectorExtractF(Context, Op.Rm, Elem, SizeF);